參數(shù)資料
型號(hào)： ADUC7129BSTZ126-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 66/92頁(yè)
文件大?。?/td> 0K
描述： IC DAS MCU ARM7 ADC/DDS 80-LQFP
產(chǎn)品培訓(xùn)模塊： ARM7 Applications & Tools
Intro to ARM7 Core & Microconverters
Process Control
Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 41.78MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： PLA，POR，PWM，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 38
程序存儲(chǔ)器容量： 126KB（63K x 16）
程序存儲(chǔ)器類(lèi)型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x12b; D/A 1x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 80-LQFP
包裝： 標(biāo)準(zhǔn)包裝
其它名稱(chēng)： ADUC7129BSTZ126-RLDKR
ADuC7128/ADuC7129
Rev. 0 | Page 69 of 92
I2CxFIF Register
Name
Address
Default Value
Access
I2C0FIF
0xFFFF084C
0x0000
R
I2C1FIF
0xFFFF094C
0x0000
R
I2CxFIF is a FIFO status register.
Table 95. I2C0FIF MMR Bit Designations
Bit
Value
Description
15:10
Reserved.
9
Master Transmit FIFO Flush.
Set by user to flush the master Tx FIFO.
Cleared automatically once the master Tx FIFO is flushed. This bit also flushes the slave receive FIFO.
8
Slave Transmit FIFO Flush.
Set by user to flush the slave Tx FIFO.
Cleared automatically once the slave Tx FIFO is flushed.
7:6
Master Rx FIFO Status Bits.
00
FIFO Empty.
01
Byte Written to FIFO.
10
1 Byte in FIFO.
11
FIFO Full.
5:4
Master Tx FIFO Status Bits.
00
FIFO Empty.
01
Byte Written to FIFO.
10
1 Byte in FIFO.
11
FIFO Full.
3:2
Slave Rx FIFO Status Bits.
00
FIFO Empty.
01
Byte Written to FIFO.
10
1 Byte in FIFO.
11
FIFO Full.
1:0
Slave Tx FIFO Status Bits.
00
FIFO Empty.
01
Byte Written to FIFO.
10
1 Byte in FIFO.
11
FIFO full.
PROGRAMMABLE LOGIC ARRAY (PLA)
The ADuC7128/ADuC7129 integrate a fully programmable
logic array (PLA) that consists of two independent but
interconnected PLA blocks. Each block consists of eight PLA
elements, giving a total of 16 PLA elements.
A PLA element contains a two input look-up table that can be
configured to generate any logic output function based on two
inputs and a flip-flop as represented in Figure 54.
4
2
0
1
3
A
B
LOOK-UP
TABLE
06
02
0-
0
49
Figure 54. PLA Element
In total, 30 GPIO pins are available on the ADuC7128/ADuC7129
for the PLA. These include 16 input pins and 14 output pins.
They need to be configured in the GPxCON register as PLA
pins before using the PLA. Note that the comparator output is
also included as one of the 16 input pins.
The PLA is configured via a set of user MMRs and the output(s)
of the PLA can be routed to the internal interrupt system, to the
CONVST signal of the ADC, to an MMR, or to any of the
16 PLA output pins.
The interconnection between the two blocks is supported by
connecting the output of Element 7 of Block 1 fed back to the
Input 0 of Mux 0 of Element 0 of Block 0, and the output of
Element 7 of Block 0 is fed back to the Input 0 of Mux 0 of
Element 0 of Block 1.
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