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| 型號： | ADUC7129BSTZ126-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 60/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAS MCU ARM7 ADC/DDS 80-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | ARM7 Applications & Tools Intro to ARM7 Core & Microconverters Process Control Direct Digital Synthesis Tutorial Series (1 of 7): Introduction |
| 標準包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 41.78MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PLA，POR，PWM，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 38 |
| 程序存儲器容量： | 126KB（63K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 10x12b; D/A 1x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 80-LQFP |
| 包裝： | 標準包裝 |
| 其它名稱： | ADUC7129BSTZ126-RLDKR |
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ADuC7128/ADuC7129
Rev. 0 | Page 63 of 92
SERIAL PERIPHERAL INTERFACE
The ADuC7128/ADuC7129 integrate a complete hardware
serial peripheral interface (SPI) on-chip. SPI is an industry-
standard synchronous serial interface that allows eight bits
of data to be synchronously transmitted and simultaneously
received, that is, full duplex up to a maximum bit rate of 3.4 Mbs.
The SPI interface is operational only with core clock divider
bits POWCON[2:0] = 0, 1, or 2.
The SPI port can be configured for master or slave operation and
typically consists of four pins, namely: MISO, MOSI, SCL, and CS.
MISO (Master In, Slave Out) Data I/O Pin
The MISO pin is configured as an input line in master mode
and an output line in slave mode. The MISO line on the master
(data in) should be connected to the MISO line in the slave
device (data out). The data is transferred as byte wide (8-bit)
serial data, MSB first.
MOSI (Master Out, Slave In) Pin
The MOSI pin is configured as an output line in master mode
and an input line in slave mode. The MOSI line on the master
(data out) should be connected to the MOSI line in the slave
device (data in). The data is transferred as byte wide (8-bit)
serial data, MSB first.
SCL (Serial Clock) I/O Pin
The master serial clock (SCL) is used to synchronize the data
being transmitted and received through the MOSI SCL period.
Therefore, a byte is transmitted/received after eight SCL periods.
The SCL pin is configured as an output in master mode and as
an input in slave mode.
In master mode, polarity and phase of the clock are controlled
by the SPICON register, and the bit rate is defined in the
SPIDIV register as follows:
)
1
(
2
SPIDIV
f
HCLK
CLOCK
SERIAL
+
×
=
In slave mode, the SPICON register must be configured with
the phase and polarity of the expected input clock. The slave
accepts data from an external master up to 3.4 Mbs at CD = 0.
In both master and slave modes, data is transmitted on one edge
of the SCL signal and sampled on the other. Therefore, it is
important that the polarity and phase be configured the same
for the master and slave devices.
The maximum speed of the SPI clock is dependent on the clock
divider bits and is summarized in Table 89.
Table 89. SPI Speed vs. Clock Divider Bits in Master Mode
CD Bits
0
1
2
3
4
5
SPIDIV in hex
0x05
0x0B
0x17
0x2F
0x5F
0xBF
SPI speed
in MHz
3.482
1.741
0.870
0.435
0.218
0.109
In slave mode, the SPICON register must be configured with
the phase and polarity of the expected input clock. The slave
accepts data from an external master up to 10.4 Mbs at CD = 0.
The formula to determine the maximum speed follows:
4
HCLK
CLOCK
SERIAL
f
=
In both master and slave modes, data is transmitted on one edge
of the SCL signal and sampled on the other. Therefore, it is
important that the polarity and phase be configured the same
for the master and slave devices.
Chip Select (CS) Input Pin
In SPI slave mode, a transfer is initiated by the assertion of CS,
which is an active low input signal. The SPI port then transmits
and receives 8-bit data until the transfer is concluded by
desassertion of CS. In slave mode, CS is always an input.
SPI Registers
The following MMR registers are used to control the SPI
interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON.
SPISTA Register
Name
Address
Default Value
Access
SPISTA
0xFFFF0A00
0x00
R
SPISTA is an 8-bit read-only status register.
Table 90. SPISTA MMR Bit Designations
Bit
Description
7:6
Reserved.
5
SPIRX Data Register Overflow Status Bit.
Set if SPIRX is overflowing.
Cleared by reading SPIRX register.
4
SPIRX Data Register IRQ.
Set automatically if Bit 3 or Bit 5 is set.
Cleared by reading SPIRX register.
3
SPIRX Data Register Full Status Bit.
Set automatically if valid data is present in the SPIRX
register.
Cleared by reading SPIRX register.
2
SPITX Data Register Underflow Status Bit.
Set automatically if SPITX is underflowing.
Cleared by writing in the SPITX register.
1
SPITX Data Register IRQ.
Set automatically if Bit 0 is clear or Bit 2 is set.
Cleared by writing in the SPITX register or if finished
transmission disabling the SPI.
0
SPITX Data Register Empty Status Bit.
Set by writing to SPITX to send data. This bit is set
during transmission of data.
Cleared when SPITX is empty.
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