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參數(shù)資料
| 型號(hào)： | ADUC7126BSTZ126IRL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 77/108頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 16/32B 126KB FLASH 80LQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 41.78MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 40 |
| 程序存儲(chǔ)器容量： | 126KB（63K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 32K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 12x12b，D/A 4x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 80-LQFP |
| 包裝： | 帶卷 (TR) |
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ADuC7124/ADuC7126
Data Sheet
Rev. C | Page 70 of 108
I2C
The ADuC7124/ADuC7126 incorporate two I2C peripherals
that can be configured as a fully I2C-compatible I2C bus master
device or as a fully I2C bus compatible slave device. Both I2C
channels are identical. Therefore, the following descriptions
apply to both channels.
The two pins used for data transfer, SDA and SCL, are configured
in a wire-AND’ed format that allows arbitration in a multimaster
system. These pins require external pull-up resistors. Typical
pull-up values are between 4.7 kΩ and 10 kΩ.
The I2C bus peripheral address in the I2C bus system is
programmed by the user. This ID can be modified any time a
transfer is not in progress. The user can configure the interface
to respond to four slave addresses.
The transfer sequence of an I2C system consists of a master
device initiating a transfer by generating a start condition while
the bus is idle. The master transmits the slave device address
and the direction of the data transfer (read or/write) during the
initial address transfer. If the master does not lose arbitration
and the slave acknowledges, the data transfer is initiated. This
continues until the master issues a stop condition and the bus
becomes idle.
The I2C peripheral can only be configured as a master or slave at
any given time. The same I2C channel cannot simultaneously
support master and slave modes.
The I2C interface on the ADuC7124/ADuC7126 includes the
following features:
Support for repeated start conditions. In master mode, the
ADuC7124/ADuC7126 can be programmed to generate a
repeated start. In slave mode, the ADuC7124/ADuC7126
recognizes repeated start conditions.
In master and slave mode, the part recognizes both 7-bit
and 10-bit bus addresses.
In I2C master mode, the ADuC7124/ADuC7126 supports
continuous reads from a single slave up to 512 bytes in a
single transfer sequence.
Clock stretching is supported in both master and slave modes.
In slave mode, the ADuC7124/ADuC7126 can be pro-
grammed to return a NACK. This allows the validiation of
checksum bytes at the end of I2C transfers.
Bus arbitration in master mode is supported.
Internal and external loopback modes are supported for
I2C hardware testing in loopback mode.
The transmit and receive circuits in both master and slave
mode contain 2-byte FIFOs. Status bits are available to the
user to control these FIFOs.
Configuring External Pins for I2C Functionality
The I2C pins of the ADuC7124/ADuC7126 device are P1.0 and
P1.1 for I2C0 and P1.2 and P1.3 for I2C1.
P1.0 and P1.2 are the I2C clock signals, and P1.1 and P1.3 are
the I2C data signals. For instance, to configure I2C0 pins (SCL0,
SDA0), Bit 0 and Bit 4 of the GP1CON register must be set to 1
to enable I2C mode. On the other hand, to configure I2C1 pins
(SCL1, SDA1), Bit 8 and Bit 12 of the GP1CON register must
Input/Output section.
Serial Clock Generation
The I2C master in the system generates the serial clock for a
transfer. The master channel can be configured to operate in
fast mode (400 kHz) or standard mode (100 kHz).
The bit rate is defined in the I2CxDIV MMR as follows:
)
(2
)
2
(
DIVL
DIVH
+
=
UCLK
CLOCK
SERIAL
f
where:
fUCLK is the clock before the clock divider.
DIVH is the high period of the clock.
DIVL is the low period of the clock.
Therefore, for 100 kHz operation,
DIVH = DIVL = 0xCF
and for 400 kHz
DIVH = 0x28, DIVL = 0x3C
The I2CxDIV register corresponds to DIVH:DIVL.
I2C Bus Addresses
Slave Mode
In slave mode, the I2CxID0, I2CxID1, I2CxID2, and I2CxID3
registers contain the device IDs. The device compares the four
I2CxIDx registers to the address byte received from the bus
master. To be correctly addressed, the seven MSBs of either ID
register must be identical to the seven MSBs of the first received
address byte. The LSB of the ID registers (the transfer direction
bit) is ignored in the process of address recognition.
The ADuC7124/ADuC7126 also support 10-bit addressing
mode. When Bit 1 of I2CxSCON (ADR10EN bit) is set to 1, one
10-bit address is supported in slave mode and is stored in the
I2CxID0 and I2CxID1 registers. The 10-bit address is derived as
follows:
I2CxID0[0] is the read/write bit and is not part of the I2C
address.
I2CxID0[7:1] = Address Bits[6:0].
I2CxID1[2:0] = Address Bits[9:7].
I2CxID1[7:3] must be set to 11110b.
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| ADUC7126BSTZ126-RL | 功能描述:IC MCU 16/32B 126KB FLASH 80LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC7xxx 標(biāo)準(zhǔn)包裝:38 系列:Encore!® XP® 核心處理器:eZ8 芯體尺寸:8-位 速度:5MHz 連通性:IrDA，UART/USART 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，LED，POR，PWM，WDT 輸入/輸出數(shù):16 程序存儲(chǔ)器容量:4KB（4K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 105°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:管件 其它名稱:269-4116Z8F0413SH005EG-ND |
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