參數資料
型號: ADUC7126BSTZ126IRL
廠商: Analog Devices Inc
文件頁數: 30/108頁
文件大?。?/td> 0K
描述: IC MCU 16/32B 126KB FLASH 80LQFP
標準包裝: 1,000
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 41.78MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設備: POR,PWM,WDT
輸入/輸出數: 40
程序存儲器容量: 126KB(63K x 16)
程序存儲器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數據轉換器: A/D 12x12b,D/A 4x12b
振蕩器型: 內部
工作溫度: -40°C ~ 125°C
封裝/外殼: 80-LQFP
包裝: 帶卷 (TR)
ADuC7124/ADuC7126
Data Sheet
Rev. C | Page 28 of 108
More information relative to the model of the programmer and
the ARM7TDMI core architecture can be found in the
following materials from ARM:
DDI0029G, ARM7TDMI Technical Reference Manual
DDI-0100, ARM Architecture Reference Manual
INTERRUPT LATENCY
The worst-case latency for a fast interrupt request (FIQ)
consists of the following:
The longest time the request can take to pass through the
synchronizer
The time for the longest instruction to complete (the
longest instruction is an LDM) that loads all the registers
including the PC
The time for the data abort entry
The time for the FIQ entry
At the end of this time, the ARM7TDMI executes the instruction
at 0x1C (FIQ interrupt vector address). The maximum total
time is 50 processor cycles, which is just under 1.2 μs in a
system using a continuous 41.78 MHz processor clock.
The maximum interrupt request (IRQ) latency calculation is
similar but must allow for the fact that FIQ has higher priority
and can delay entry into the IRQ handling routine for an
arbitrary length of time. This time can be reduced to 42 cycles if
the LDM command is not used. Some compilers have an option
to compile without using this command. Another option is to run
the part in Thumb mode where the time is reduced to 22 cycles.
The minimum latency for FIQ or IRQ interrupts is a total of
five cycles, which consist of the shortest time the request can
take through the synchronizer plus the time to enter the
exception mode.
Note that the ARM7TDMI always runs in ARM (32-bit) mode
when in privileged modes, for example, when executing interrupt
service routines.
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