參數(shù)資料
型號: ADUC7126BSTZ126IRL
廠商: Analog Devices Inc
文件頁數(shù): 68/108頁
文件大?。?/td> 0K
描述: IC MCU 16/32B 126KB FLASH 80LQFP
標(biāo)準(zhǔn)包裝: 1,000
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 41.78MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 40
程序存儲器容量: 126KB(63K x 16)
程序存儲器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x12b,D/A 4x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 80-LQFP
包裝: 帶卷 (TR)
ADuC7124/ADuC7126
Data Sheet
Rev. C | Page 62 of 108
COM1DIV0 Register
Name:
COM1DIV0
Address:
0xFFFF0740
Default Value:
0x00
Access:
Read/write
COM1DIV0 is a low byte divisor latch for UART1. COM1TX,
COM1RX, and COM1DIV0 share the same address location.
COM1TX and COM1RX can be accessed when Bit 7 in
COM1CON0 register is cleared. COM1DIV0 can be accessed
when Bit 7 of COM1CON0 is set.
COM0IEN0 Register
Name:
COM0IEN0
Address:
0xFFFF0704
Default Value:
0x00
Access:
Read/write
COM0IEN0 is the interrupt enable register for UART0.
COM1IEN0 Register
Name:
COM1IEN0
Address:
0xFFFF0744
Default Value:
0x00
Access:
Read/write
COM1IEN0 is the interrupt enable register for UART1.
Table 92. COMxIEN0 MMR Bit Descriptions
Bit
Name
Description
[7:4]
Reserved.
3
EDSSI
Modem status interrupt enable bit.
Set by the user to enable generation of an
interrupt if any of COMXSTA1[3:1] are set.
Cleared by the user.
2
ELSI
Rx status interrupt enable bit.
Set by the user to enable generation of an
interrupt if any of COMxSTA0[3:0] are set.
Cleared by the user.
1
ETBEI
Enable transmit buffer empty interrupt.
Set by the user to enable interrupt when the
buffer is empty during a transmission.
Cleared by the user.
0
ERBFI
Enable receive buffer full interrupt.
In non-FIFO mode, set by the user to enable
an interrupt when buffer is full during a
reception. Cleared by the user.
In FIFO mode, set by the user to enable an
interrupt when trigger level is reached. It also
controls the character receive timeout
interrupt. Cleared by the user.
COM0DIV1 Register
Name:
COM0DIV1
Address:
0xFFFF0704
Default Value:
0x00
Access:
Read/write
COM0DIV1 is a divisor latch (high byte) register for UART0.
COM1DIV1 Register
Name:
COM1DIV1
Address:
0xFFFF0744
Default Value:
0x00
Access:
Read/write
COM1DIV1 is a divisor latch (high byte) register for UART1.
COM0IID0 Register
Name:
COM0IID0
Address:
0xFFFF0708
Default Value:
0x01
Access:
Read only
COM0IID0 is the interrupt identification register for UART0. It
also indicates if the UART is in FIFO mode.
COM1IID0 Register
Name:
COM1IID0
Address:
0xFFFF0748
Default Value:
0x01
Access:
Read only
COM1IID0 is the interrupt identification register for UART1. It
also indicates if the UART is in FIFO mode.
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