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參數(shù)資料
型號: ADUC7124BCPZ126-RL
廠商: Analog Devices Inc
文件頁數(shù): 81/108頁
文件大?。?/td> 0K
描述: IC DAS MCU ARM7 ADC/DDS 64-LQFP
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
標(biāo)準(zhǔn)包裝: 2,500
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 41.78MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 30
程序存儲器容量: 126KB(63K x 16)
程序存儲器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x12b; D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 64-LFQFN 裸露焊盤,CSP
包裝: 帶卷 (TR)
ADuC7124/ADuC7126
Data Sheet
Rev. C | Page 74 of 108
I2C Address 1 Register
Name:
I2C0ADR1, I2C1ADR1
Address:
0xFFFF081C, 0xFFFF091C
Default Value:
0x00
Access:
Read/write
Function:
This 8-bit MMR is used in 10-bit addressing
mode only. This register contains the least
significant byte of the address.
Table 107. I2CxADR1 MMR in 10-Bit Address Mode
Bit
Name
Description
[7:0]
I2CLADR
These bits contain ADDR[7:0] in 10-bit
addressing mode.
I2C Master Clock Control Register
Name:
I2C0DIV, I2C1DIV
Address:
0xFFFF0824, 0xFFFF0924
Default Value:
0x1F1F
Access:
Read/write
Function:
This MMR controls the frequency of the I2C
clock generated by the master on to the SCL
pin. For further details, see the I2C section.
Table 108. I2CxDIV MMR
Bit
Name
Description
[15:8]
DIVH
These bits control the duration of the high
period of SCL.
[7:0]
DIVL
These bits control the duration of the low
period of SCL.
I2C Slave Registers
I2C Slave Control Register
Name:
I2C0SCON, I2C1SCON
Address:
0xFFFF0828, 0xFFFF0928
Default Value:
0x0000
Access:
Read/write
Function:
This 16-bit MMR configures the I2C
peripheral in slave mode.
Table 109. I2CxSCON MMR Bit Descriptions
Bit
Name
Description
[15:11]
Reserved.
10
I2CSTXENI
Slave transmit interrupt enable bit.
Set this bit to enable an interrupt after a slave transmits a byte.
Clear this interrupt source.
9
I2CSRXENI
Slave receive interrupt enable bit.
Set this bit to enable an interrupt after the slave receives data.
Clear this interrupt source.
8
I2CSSENI
I2C stop condition detected interrupt enable bit.
Set this bit to enable an interrupt on detecting a stop condition on the I2C bus.
Clear this interrupt source.
7
I2CNACKEN
I2C NACK enable bit.
Set this bit to NACK the next byte in the transmission sequence.
Clear this bit to let the hardware control the ACK/NACK sequence.
6
I2CSSEN
I2C slave SCL stretch enable bit.
Set this bit to 1 to enable clock stretching. When SCL is low, setting this bit forces the device to hold SCL low
until I2CSSEN is cleared. If SCL is high, setting this bit forces the device to hold SCL low after the next falling
edge.
Clear this bit to disable clock stretching.
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