參數(shù)資料
型號： ADUC7124BCPZ126-RL
廠商： Analog Devices Inc
文件頁數(shù)： 71/108頁
文件大?。?/td> 0K
描述： IC DAS MCU ARM7 ADC/DDS 64-LQFP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
標(biāo)準(zhǔn)包裝： 2,500
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 41.78MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 30
程序存儲器容量： 126KB（63K x 16）
程序存儲器類型： 閃存
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x12b; D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 64-LFQFN 裸露焊盤，CSP
包裝： 帶卷 (TR)
Data Sheet
ADuC7124/ADuC7126
Rev. C | Page 65 of 108
COM1STA0 Register
Name:
COM1STA0
Address:
0xFFFF0754
Default Value:
0xE0
Access:
Read only
COM1STA0 is the line status register for UART1.
Table 97. COMxSTA0 MMR Bit Descriptions
Bit
Name
Description
11
RX_error
Set automatically if PE, FE, or BI is set.
Cleared automatically when PE, FE, and
BI are cleared .
10
RX_timeout
Only for FIFO mode. Set automatically if
there is at least one byte in the Rx FIFO
and there is no access to the Rx FIFO in
the next 4-byte accessing cycle.
9
RX_triggered
Only for FIFO mode. Set automatically if
the Rx FIFO number exceeds the trigger
level, which is configured by the FIFO
control register COMxFCR[7:5]. Cleared
automatically when the Rx FIFO number
is equal to or less than the trigger level.
8
TX_full
Only for FIFO mode. Set automatically if
Tx FIFO is full. Cleared automatically
when Tx FIFO is not full.
7
TX_half_empty
Only for FIFO mode. Set automatically if
the Tx FIFO is half empty (number of
bytes in Tx FIFO ≤ 8). Cleared automati-
cally when the Tx FIFO received bytes is
more than eight bytes.
6
TEMT
COMxTX empty status bit.
For non-FIFO mode, both THR and TSR
are empty.
For FIFO mode, both Tx FIFO and TSR are
empty.
5
THRE
COMxTX and transmitter shift register
empty.
For non-FIFO mode, transmitter hold
register (THR) empty or the content of
THR has been transferred to the
transmitter shift register (TSR).
For FIFO mode, Tx FIFO is empty, or the
last character in the FIFO has been
transferred to the transmitter shift
register (TSR).
4
BI
Break error.
Set when SINx is held low for more than
the maximum word length.
Cleared automatically.
3
FE
Framing error.
Set when an invalid stop bit occurs.
Cleared automatically.
2
PE
Parity error.
Set when a parity error occurs.
Cleared automatically.
Bit
Name
Description
1
OE
Overrun error.
For non-FIFO mode, set automatically if
data is overwritten before being read.
Cleared automatically.
For FIFO mode, set automatically if an
overrun error has been detected. An
overrun error occurs only after the FIFO
is full and the next character has been
completely received in the shift register.
The new character overwrites the
character in the shift register, but it is
not transferred to the FIFO.
0
DR
Data ready.
For non-FIFO mode, set automatically
when COMxRX is full. Cleared by reading
COMxRX.
For FIFO mode, set automatically when
there is at least one unread byte in the
COMxRX.
COM0STA1 Register
Name:
COM0STA1
Address:
0xFFFF0718
Default Value:
0x00
Access:
Read only
COM0STA1 is a modem status register.
COM1STA1 Register
Name:
COM1STA1
Address:
0xFFFF0758
Default Value:
0x00
Access:
Read only
COM1STA1 is a modem status register.
Table 98. COMxSTA1 MMR Bit Descriptions
Bit
Name
Description
7
DCD
Data carrier detect.
6
RI
Ring indicator.
5
DSR
Data set ready.
4
CTS
Clear to send.
3
DDCD
Delta DCD. Set automatically if DCD changed
state since last COMxSTA1 read. Cleared
automatically by reading COMxSTA1.
2
TERI
Trailing edge RI. Set if RI changed from 0 to 1
since COMxSTA1 last read. Cleared automatically
by reading COMxSTA1.
1
DDSR
Delta DSR. Set automatically if DSR changed state
since COMxSTA1 last read. Cleared automatically
by reading COMxSTA1.
0
DCTS
Delta CTS. Set automatically if CTS changed state
since COMxSTA1 last read. Cleared automatically
by reading COMxSTA1.
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