參數(shù)資料
型號: ADUC7124BCPZ126-RL
廠商: Analog Devices Inc
文件頁數(shù): 73/108頁
文件大?。?/td> 0K
描述: IC DAS MCU ARM7 ADC/DDS 64-LQFP
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
標(biāo)準(zhǔn)包裝: 2,500
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 41.78MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 30
程序存儲器容量: 126KB(63K x 16)
程序存儲器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x12b; D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 64-LFQFN 裸露焊盤,CSP
包裝: 帶卷 (TR)
Data Sheet
ADuC7124/ADuC7126
Rev. C | Page 67 of 108
SPI Registers
The following MMR registers control the SPI interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON.
SPI Status Register
Name:
SPISTA
Address:
0xFFFF0A00
Default Value:
0x0000
Access:
Read only
Function:
This 32-bit MMR contains the status of the SPI interface in both master and slave modes.
Table 100. SPISTA MMR Bit Descriptions
Bit
Name
Description
[15:12]
Reserved.
11
SPIREX
SPI Rx FIFO excess bytes present. This bit is set when there are more bytes in the Rx FIFO than indicated in the
SPIMDE bits in SPICON
This bit is cleared when the number of bytes in the FIFO is equal to or less than the number in SPIMDE.
[10:8]
SPIRXFSTA[2:0]
SPI Rx FIFO status bits.
[000] = Rx FIFO is empty.
[001] = one valid byte in the FIFO.
[010] = two valid bytes in the FIFO.
[011] = three valid bytes in the FIFO.
[100] = four valid bytes in the FIFO.
7
SPIFOF
SPI Rx FIFO overflow status bit.
Set when the Rx FIFO was already full when new data was loaded to the FIFO. This bit generates an interrupt
except when SPIRFLH is set in SPICON.
Cleared when the SPISTA register is read.
6
SPIRXIRQ
SPI Rx IRQ status bit.
Set when a receive interrupt occurs. This bit is set when SPITMDE in SPICON is cleared and the required
number of bytes has been received.
Cleared when the SPISTA register is read.
SPITXIRQ
SPI Tx IRQ status bit.
Set when a transmit interrupt occurs. This bit is set when SPITMDE in SPICON is set and the required number
of bytes has been transmitted.
5
Cleared when the SPISTA register is read.
4
SPITXUF
SPI Tx FIFO underflow.
This bit is set when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt
except when SPITFLH is set in SPICON.
Cleared when the SPISTA register is read.
[3:1]
SPITXFSTA[2:0]
SPI Tx FIFO status bits.
[000] = Tx FIFO is empty.
[001] = one valid byte in the FIFO.
[010] = two valid bytes in the FIFO.
[011] = three valid bytes in the FIFO.
[100] = four valid bytes in the FIFO.
0
SPIISTA
SPI interrupt status bit.
Set to 1 when an SPI-based interrupt occurs.
Cleared after reading SPISTA.
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