參數(shù)資料
型號(hào)： ADUC7124BCPZ126-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 69/108頁(yè)
文件大?。?/td> 0K
描述： IC DAS MCU ARM7 ADC/DDS 64-LQFP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
標(biāo)準(zhǔn)包裝： 2,500
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 41.78MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 30
程序存儲(chǔ)器容量： 126KB（63K x 16）
程序存儲(chǔ)器類(lèi)型： 閃存
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x12b; D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 64-LFQFN 裸露焊盤(pán)，CSP
包裝： 帶卷 (TR)
Data Sheet
ADuC7124/ADuC7126
Rev. C | Page 63 of 108
Table 93. COMxIID0 MMR Bit Descriptions
Bit
Name
Description
[7:6]
FIFOMODE
FIFO mode flag.
0x0: non-FIFO mode.
0x1: reserved.
0x2: reserved.
0x3: FIFO mode. Set automatically if
FIFOEN is set.
[5:4]
Reserved
[3:1]
STATUS[2:0]
Interrupt status bits that work only when
NINT is set.
[000]: modem status interrupt. Cleared by
reading COMxSTA1. Priority 4.
[001]: for non-FIFO mode, transmit buffer
empty interrupt.
For FIFO mode, Tx FIFO is empty.
Cleared by writing COMxTX or reading
COMxIID0. Priority 3.
[010]: non-FIFO mode. Receive buffer data
ready interrupt. Cleared automatically by
reading COMxRX.
For FIFO mode, set trigger level reached.
Cleared automatically when FIFO drops
below the trigger level. Priority 2.
[011]: receive line status error interrupt.
Cleared by reading COMxSTA0. Priority 1.
[110]: Rx FIFO timeout interrupt (FIFO
mode only). Set automatically if there is at
least one byte in the Rx FIFO, and there is
no access to the Rx FIFO in the next four-
frames accessing cycle. Cleared by reading
COMxRX, setting RXRST, or when a new
byte arrives in the Rx FIFO1. Priority 2.
[Other state]: reserved.
0
NINT
Set to disable interrupt flags by
STATUS[2:0]. Clear to enable interrupt.
1 A frame time is the time allotted for one start bit, n data bits, one parity bit,
and one stop bit. Here, n is the word length selected with the WLS bits in
COMxCON0.
WLS[1:0] = 00: timeout threshold = time for 32 bits = (1 + 5 + 1 + 1) × 4.
WLS[1:0] = 01: timeout threshold = time for 36 bits = (1 + 6 + 1 + 1) × 4.
WLS[1:0] = 10: timeout threshold = time for 40 bits = (1 + 7 + 1 + 1) × 4.
WLS[1:0] = 11: timeout threshold = time for 44 bits = (1 + 8 + 1 + 1) × 4.
COM0FCR Register
Name:
COM0FCR
Address:
0xFFFF0708
Default Value:
0x00
Access:
Read/write
The FIFO control register (FCR) is a write-only register at the
same address as the interrupt identification register (IIR), which
is a read-only register.
COM1FCR Register
Name:
COM1FCR
Address:
0xFFFF0748
Default Value:
0x00
Access:
Read/write
The FIFO control register (FCR) is a write-only register at the
same address as the interrupt identification register (IIR), which
is a read-only register.
Table 94. COMxFCR MMR Bit Descriptions
Bit
Name
Description
[7:5]
RXFIFOTL
Receiver FIFO trigger level. RXFIFOTL sets the
trigger level for the receiver FIFO. When the
trigger level is reached, a receiver data-ready
interrupt is generated (if the interrupt
request is enabled). When the FIFO drops
below the trigger level, the interrupt is
cleared.
0x0: one byte.
0x1: two bytes.
0x2: four bytes.
0x3: six bytes.
0x4: eight bytes.
0x5: 10 bytes.
0x6: 12 bytes.
0x7: 14 bytes.
[4:3]
Reserved
2
TXRST
Tx FIFO reset. Writing a 1 flushes the Tx FIFO.
Does not affect shift register. Note that
TXRST should be cleared manually to make
Tx FIFO work after flushing.
1
RXRST
Rx FIFO reset. Writing a 1 flushes the Rx FIFO.
Does not affect shift register. Note that
RXRST should be cleared manually to make
the Rx FIFO work after flushing.
0
FIFOEN
Transmitter and receiver FIFOs mode enable.
FIFOEN must be set before other FCR bits are
written to. Set for FIFO mode. The transmitter
and receiver FIFOs are enabled. Cleared for
non-FIFO mode; the transmitter and receiver
FIFOs are disabled, and the FIFO pointers are
cleared.
COM0CON0 Register
Name:
COM0CON0
Address:
0xFFFF070C
Default Value:
0x00
Access:
Read/write
COM0CON0 is the line control register for UART0.
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