參數(shù)資料
型號(hào)： ADSP2185
廠商： Analog Devices, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DSP Microcomputer
中文描述： DSP微機(jī)
文件頁(yè)數(shù)： 7/32頁(yè)
文件大小： 289K
代理商： ADSP2185
ADSP-2185
–7–
REV. 0
T he ADSP-2185 uses an input clock with a frequency equal to
half the instruction rate; a 16.67 MHz input clock yields a 30 ns
processor cycle (which is equivalent to 33 MHz). Normally,
instructions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLK OUT signal when enabled.
Because the ADSP-2185 includes an on-chip oscillator circuit,
an external crystal may be used. T he crystal should be con-
nected across the CLK IN and X T AL pins, with two capacitors
connected as shown in Figure 3. Capacitor values are dependent
on crystal type and should be specified by the crystal manufac-
turer. A parallel-resonant, fundamental frequency, microproces-
sor-grade crystal should be used.
A clock output (CL K OUT ) signal is generated by the proces-
sor at the processor’s cycle rate. T his can be enabled and
disabled by the CL K ODIS bit in the SPORT 0 Autobuffer
Control Register.
CLKIN
CLKOUT
XTAL
DSP
Figure 3. External Crystal Connections
Reset
T he
RESET
signal initiates a master reset of the ADSP-2185.
T he
RESET
signal must be asserted during the power-up
sequence to assure proper initialization.
RESET
during initial
power-up must be held long enough to allow the internal clock
to stabilize. If
RESET
is activated any time after power-up, the
clock continues to run and does not require stabilization time.
T he power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V
DD
is
applied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLK IN cycles ensures that the PLL has locked, but does
not include the crystal oscillator start-up time. During this
power-up sequence the
RESET
signal should be held low. On
any subsequent resets, the
RESET
signal must meet the mini-
mum pulse width specification, t
RSP
.
T he
RESET
input contains some hysteresis; however, if you use
an RC circuit to generate your
RESET
signal, the use of an
external Schmidt trigger is recommended.
T he master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MST AT
register. When
RESET
is released, if there is no pending bus
request and the chip is configured for booting, the boot-loading
sequence is performed. T he first instruction is fetched from
on-chip program memory location 0x0000 once boot loading
completes.
ME MORY ARCHIT E CT URE
T he ADSP-2185 provides a variety of memory and peripheral
interface options. T he key functional groups are Program Memory,
Data Memory, Byte Memory and I/O.
Program Memory
is a 24-bit-wide space for storing both
instruction opcodes and data. T he ADSP-2185 has 16K words
of Program Memory RAM on chip, and the capability of access-
ing up to two 8K external memory overlay spaces using the
external data bus. Both an instruction opcode and a data value
can be read from on-chip program memory in a single cycle.
Data Memory
is a 16-bit-wide space used for the storage of
data variables and for memory-mapped control registers. T he
ADSP-2185 has 16K words on Data Memory RAM on chip,
consisting of 16,352 user-accessible locations and 32 memory-
mapped registers. Support also exists for up to two 8K external
memory overlay spaces through the external data bus.
Byte Memory
(Full Memory Mode)
provides access to an
8-bit wide memory space through the Byte DMA (BDMA) port.
T he Byte Memory interface provides access to 4 MBytes of
memory by utilizing eight data lines as additional address lines.
T his gives the BDMA Port an effective 22-bit address range. On
power-up, the DSP can automatically load bootstrap code from
byte memory.
I/O Space
(Full Memory Mode)
allows access to 2048 loca-
tions of 16-bit-wide data. It is intended to be used to communi-
cate with parallel peripheral devices such as data converters and
external registers or latches.
Program Memory
T he ADSP-2185 contains a 16K
×
24 on-chip program RAM.
T he on-chip program memory is designed to allow up to two
accesses each cycle so that all operations can complete in a
single cycle. In addition, the ADSP-2185 allows the use of 8K
external memory overlays.
T he program memory space organization is controlled by the
Mode B pin and the PMOVLAY register. Normally, the ADSP-
2185 is configured with Mode B = 0 and program memory
organized as shown in Figure 4.
8K INTERNAL
(PMOVLAY = 0,
MODE B = 0)
OR
EXTERNAL 8K
(PMOVLAY = 1 or 2,
MODE B = 0)
0x3FFF
0x2000
0x1FFF
8K INTERNAL
0x0000
PROGRAM MEMORY
ADDRESS
Figure 4. Program Memory (Mode B = 0)
T here are 16K words of memory accessible internally when the
PMOVLAY register is set to 0. When PMOVLAY is set to some-
thing other than 0, external accesses occur at addresses 0x2000
through 0x3FFF. T he external address is generated as shown in
T able II.
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