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參數(shù)資料
| 型號： | ADSP2185 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | DSP微機(jī) |
| 文件頁數(shù)： | 5/32頁 |
| 文件大小： | 289K |
| 代理商： | ADSP2185 |
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ADSP-2185
–5–
REV. 0
RESET is deasserted, the driver should three-state, thus allow-
ing full use of the PF2 pin as either an input or output.
T o minimize power consumption during power-down, configure
the programmable flag as an output when connected to a three-
stated buffer. T his ensures that the pin will be held at a constant
level and not oscillate should the three-state driver’s level hover
around the logic switching point.
Interrupts
T he interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
T he ADSP-2185 provides four dedicated external interrupt
input pins,
IRQ2
,
IRQL0
,
IRQL1
and
IRQE
(shared with the
PF7:4 pins). In addition, SPORT 1 may be reconfigured for
IRQ0
,
IRQ1
, FLAG_IN and FLAG_OUT , for a total of six
external interrupts. T he ADSP-2185 also supports internal
interrupts from the timer, the byte DMA port, the two serial
ports, software and the power-down control circuit. T he inter-
rupt levels are internally prioritized and individually maskable
(except power-down and reset). T he
IRQ2
,
IRQ0
and
IRQ1
input pins can be programmed to be either level- or edge-sensitive.
IRQL0
and
IRQL1
are level-sensitive and IRQE is edge-sensitive.
T he priorities and vector addresses of all interrupts are shown in
T able I.
T able I. Interrupt Priority & Interrupt Vector Addresses
Source Of Interrupt
Interrupt Vector Address (Hex)
Reset (or Power-Up with
PUCR = 1)
Power-down (Nonmaskable)
IRQ2
IRQL1
IRQL0
SPORT 0 T ransmit
SPORT 0 Receive
IRQE
BDMA Interrupt
SPORT 1 T ransmit or
IRQ1
SPORT 1 Receive or
IRQ0
T imer
0000 (Highest Priority)
002C
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028 (Lowest Priority)
Interrupt routines can either be nested, with higher priority
interrupts taking precedence, or processed sequentially. Inter-
rupts can be masked or unmasked with the IMASK register.
Individual interrupt requests are logically ANDed with the bits
in IMASK ; the highest priority unmasked interrupt is then
selected. T he power-down interrupt is nonmaskable.
T he ADSP-2185 masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. T his does not affect serial port autobuffering
or DMA transfers.
T he interrupt control register, ICNT L, controls interrupt nest-
ing and defines the
IRQ0
,
IRQ1
and
IRQ2
external interrupts to
be either edge- or level-sensitive. T he
IRQE
pin is an external
edge-sensitive interrupt and can be forced and cleared. T he
IRQL0
and
IRQL1
pins are external level-sensitive interrupts.
T he IFC register is a write-only register used to force and clear
interrupts.
On-chip stacks preserve the processor status and are automati-
cally maintained during interrupt handling. T he stacks are twelve
levels deep to allow interrupt, loop and subroutine nesting.
T he following instructions allow global enable or disable servic-
ing of the interrupts (including power-down), regardless of the
state of IMASK . Disabling the interrupts does not affect serial
port autobuffering or DMA.
ENA INTS;
DIS INTS;
When the processor is reset, interrupt servicing is enabled.
LOW POWE R OPE RAT ION
T he ADSP-2185 has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. T hese modes are:
Power-Down
Idle
Slow Idle
T he CLK OUT pin may also be disabled to reduce external
power dissipation.
Power-Down
T he ADSP-2185 processor has a low power feature that lets the
processor enter a very low power dormant state through hard-
ware or software control. Here is a brief list of power-down
features. Refer to the
ADSP-2100 Family User’s Manual
, “System
Interface” chapter, for detailed information about the power-
down feature.
Quick recovery from power-down. T he processor begins
executing instructions in as few as 100 CLK IN cycles.
Support for an externally generated T T L or CMOS proces-
sor clock. T he external clock can continue running during
power-down without affecting the lowest power rating and
100 CLK IN cycle recovery.
Support for crystal operation includes disabling the oscillator
to save power (the processor automatically waits approxi-
mately 4096 CLK IN cycles for the crystal oscillator to start
or stabilize), and letting the oscillator run to allow 100CLK IN
cycle start-up.
Power-down is initiated by either the power-down pin (
PWD
)
or the software power-down force bit.
Interrupt support allows an unlimited number of instructions
to be executed before optionally powering down. T he power-
down interrupt also can be used as a nonmaskable, edge-
sensitive interrupt.
Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving the
power-down state.
T he
RESET
pin also can be used to terminate power-down.
Power-down acknowledge pin indicates when the processor
has entered power-down.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-2185 | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer |
| ADSP-2185BST-115 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 28.8MHz 28.8MIPS 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:DSP,5V,28MHZ,32K WORD RAM, 100TQFP - Bulk |
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