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參數(shù)資料
| 型號： | ADSP2185 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | DSP微機 |
| 文件頁數(shù)： | 6/32頁 |
| 文件大?。?/td> | 289K |
| 代理商： | ADSP2185 |
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ADSP-2185
–6–
REV. 0
Idle
When the ADSP-2185 is in the Idle Mode, the processor waits
indefinitely in a low power state until an interrupt occurs. When
an unmasked interrupt occurs, it is serviced; execution then
continues with the instruction following the IDLE instruction.
In Idle mode IDMA, BDMA and autobuffer cycle steals still
occur.
Slow Idle
T he IDLE instruction is enhanced on the ADSP-2185 to let the
processor’s internal clock signal be slowed, further reducing
power consumption. T he reduced clock frequency, a program-
mable fraction of the normal clock rate, is specified by a select-
able divisor given in the IDLE instruction. T he format of the
instruction is
IDLE (n);
where
n
= 16, 32, 64 or 128. T his instruction keeps the proces-
sor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals,
such as SCLK , CLK OUT and timer clock, are reduced by the
same ratio. T he default form of the instruction, when no clock
divisor is given, is the standard IDLE instruction.
When the
IDLE (n)
instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to in-
coming interrupts. T he one-cycle response time of the standard
idle state is increased by n, the clock divisor. When an enabled
interrupt is received, the ADSP-2185 will remain in the idle
state for up to a maximum of
n
processor cycles (
n
= 16, 32, 64
or 128) before resuming normal operation.
When the
IDLE (n)
instruction is used in systems that have an
externally generated serial clock (SCLK ), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of
n
processor cycles).
SY ST E M INT E RFACE
Figure 2 shows typical basic system configurations with the
ADSP-2185, two serial devices, a byte-wide EPROM and optional
external program and data overlay memories (mode selectable).
Programmable wait state generation allows the processor to
easily connect to slow peripheral devices. T he ADSP-2185 also
provides four external interrupts and two serial ports or six
external interrupts and one serial port.
Host Memory mode allows access to the full external data bus,
but limits addressing to a single address bit (A0). Additional
system peripherals can be added in this mode through the use of
external hardware to generate and latch address signals.
1/2x CLOCK
OR
CRYSTAL
SERIAL
SERIAL
DEVICE
SCLK1
RFS1 OR
IRQ0
TFS1 OR
IRQ1
DT1 OR FO
SCLK0
TFS0
DT0
SPORT0
A0-A21
DATA
CS
BYTE
MEMORY
I/O SPACE
(PERIPHERALS)
2048 LOCATIONS
CS
DATA
ADDR
DATA
ADDR
OVERLAY
MEMORY
TWO 8K
PM SEGMENTS
DM TWO 8K
D
23-0
A
13-0
D
23-8
A
10-0
D
15-8
D
23-16
A
13-0
14
24
FL0-2
PF3
CLKIN
XTAL
ADDR13-0
DATA23-0
BMS
IOMS
PMS
DMS
CMS
BR
BG
BGH
PWD
PWDACK
ADSP-2185
1/2x CLOCK
CROR
SERIAL
DEVICE
ISYOR
μCONTROLLER
16
1
16
SCLK1
IRQ0
DT1 OR FO
SCLK0
RFS0
IAD15-0
IDMA PORT
/D6
IRD
/D7
IS
IA/D4
IACK
/D3
FL0-2
PF3
CLKIN
XTAL
A0
DATA23-0
BMS
IOMS
PMS
DMS
CMS
BR
BG
BGH
PWD
PWDACK
ADSP-2185
IRQ2
/PF7
IRQE
/PF4
IRQL0
/PF5
IRQL1
/PF6
MODE C/PF2
MODE B/PF1
MODE A/PF0
HOST MEMORY MODE
IRQ2
/PF7
IRQE
/PF4
IRQL0
/PF5
IRQL1
/PF6
MODE C/PF2
MODE B/PF1
MODE A/PF0
HOST MEMORY MODE
SERIAL
Figure 2. Basic System Configuration
Clock Signals
T he ADSP-2185 can be clocked by either a crystal or a T T L-
compatible clock signal.
T he CLK IN input cannot be halted, changed during operation
or operated below the specified frequency during normal opera-
tion. T he only exception is while the processor is in the power-
down state. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual
, for detailed information on
this power-down feature.
If an external clock is used, it should be a T T L-compatible
signal running at half the instruction rate. T he signal is con-
nected to the processor’s CLK IN input. When an external clock
is used, the X T AL input must be left unconnected.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-2185 | 制造商:AD 制造商全稱:Analog Devices 功能描述:DSP Microcomputer |
| ADSP-2185BST-115 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 28.8MHz 28.8MIPS 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:DSP,5V,28MHZ,32K WORD RAM, 100TQFP - Bulk |
| ADSP-2185BST-133 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 33.3MHz 33.3MIPS 100-Pin LQFP 制造商:Analog Devices 功能描述:IC MICROCOMPUTER 32-BIT 制造商:Analog Devices 功能描述:DIGITAL SIGNAL PROCESSOR IC, DSP Type:Floating Point, Package / Case:100-TQFP, S |
| ADSP-2185BSTZ-133 | 功能描述:IC DSP CONTROLLER 16BIT 100TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:ADSP-21xx 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-2185BSTZ-133 | 制造商:Analog Devices 功能描述:IC 16-BIT MICROCOMPUTER |
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