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參數(shù)資料
| 型號： | ADSP2185 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | DSP微機 |
| 文件頁數(shù)： | 12/32頁 |
| 文件大?。?/td> | 289K |
| 代理商： | ADSP2185 |
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ADSP-2185
–12–
REV. 0
T arget Board Connector for E Z-ICE
* Probe
T he EZ-ICE
* connector (a standard pin strip header) is shown
in Figure 7. You must add this connector to your target board
design if you intend to use the EZ-ICE
*. Be sure to allow
enough room in your system to fit the EZ-ICE
* probe onto the
14-pin connector.
×
1
2
3
4
5
6
7
8
9
10
11
12
13
14
GND
KEY (NO PIN)
RESET
BR
BG
TOP VIEW
EBG
EBR
ELOUT
EE
EINT
ELIN
ECLK
EMS
ERESET
Figure 7. Target Board Connector for EZ-ICE
*
T he 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-
tion—you must remove Pin 7 from the header. T he pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spac-
ing should be 0.1
×
0.1 inches. T he pin strip header must have
at least 0.15 inch clearance on all sides to accept the EZ-ICE
*
probe plug. Pin strip headers are available from vendors such as
3M, McK enzie and Samtec.
T arget Memory Interface
For your target system to be compatible with the EZ-ICE
*
emulator, it must comply with the memory interface guidelines
listed below.
PM, DM, BM, IOM and CM
Design your Program Memory (PM), Data Memory (DM), Byte
Memory (BM), I/O Memory (IOM) and Composite Memory
(CM) external interfaces to comply with worst case device tim-
ing requirements and switching characteristics as specified in
this DSP’s data sheet. T he performance of the EZ-ICE
*
may
approach published worst case specification for some memory
access timing requirements and switching characteristics.
Note: If your target does not meet the worst case chip specifica-
tion for memory access parameters, you may not be able to
emulate your circuitry at the desired CLK IN frequency. Depend-
ing on the severity of the specification violation, you may have
trouble manufacturing your system as DSP components statisti-
cally vary in switching characteristic and timing requirements
within published limits.
Restriction: All memory strobe signals on the ADSP-2185 (
RD
,
WR
,
PMS
,
DMS
,
BMS
,
CMS
and
IOMS
) used in your target
system must have 10 k
pull-up resistors connected when the
EZ-ICE
* is being used. T he pull-up resistors are necessary
because there are no internal pull-ups to guarantee their state
during prolonged three-state conditions resulting from typical
EZ-ICE
* debugging sessions. T hese resistors may be removed
at your option when the EZ-ICE
* is not being used.
T arget System Interface Signals
When the EZ-ICE
* board is installed, the performance on
some system signals change. Design your system to be compat-
ible with the following system interface signal changes intro-
duced by the EZ-ICE
* board:
EZ-ICE
* emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the
RESET
signal.
EZ-ICE
* emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the
BR
signal.
EZ-ICE
* emulation ignores
RESET
and
BR
when single-
stepping.
EZ-ICE
* emulation ignores
RESET
and
BR
when in Emu-
lator Space (DSP halted).
EZ-ICE
* emulation ignores the state of target
BR
in certain
modes. As a result, the target system may take control of the
DSP’s external memory bus only if bus grant (
BG
) is asserted
by the EZ-ICE
* board’s DSP.
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