- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1900 > ADSP-BF526KBCZ-4C2 (Analog Devices Inc)IC DSP CTRLR 400MHZ 289CSPBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | ADSP-BF526KBCZ-4C2 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 33/36頁 |
| 文件大小： | 0K |
| 描述： | IC DSP CTRLR 400MHZ 289CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Blackfin® |
| 類型： | 定點(diǎn) |
| 接口： | DMA，以太網(wǎng)，I²C，PPI，SPI，SPORT，UART，USB |
| 時(shí)鐘速率： | 400MHz |
| 非易失內(nèi)存： | ROM（32 kB） |
| 芯片上RAM： | 132kB |
| 電壓 - 輸入/輸出： | 1.8V，2.5V，3.3V |
| 電壓 - 核心： | 1.30V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 289-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 289-CSPBGA（12x12） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁當(dāng)前第33頁第34頁第35頁第36頁
Rev. A
|
Page 6 of 36
|
March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
The programmer can simultaneously load the volume control of
both channels by writing to the LRHPBOTH (Register R2, Bit
D8) and RLHPBOTH (Register R3, Bit D8) bits of the left- or
right-channel DAC volume registers.
The maximum output level of the headphone outputs is
1.0 V rms when AVDD and HPVDD = 3.3 V. To suppress audi-
ble pops and clicks, the headphone and line outputs are held at
the VMID dc voltage level when the device is set to standby
mode or when the headphone outputs are muted.
The stereo line outputs of the codec, the LOUT and ROUT pins,
can drive a load impedance of 10 k
Ω and 50 pF. The line output
signal levels are not adjustable at the output mixer, which has a
fixed gain of 0 dB. The maximum output level of the line out-
puts is 1.0 V rms when AVDD = 3.3 V.
DIGITAL AUDIO INTERFACE
The digital audio input can support the following digital audio
communication protocols: right-justified mode, left-justified
through Figure 10 on Page 7.
The mode selection is performed by writing to the FORMAT
bits of the digital audio interface register (Register R7, Bit D1
and Bit D0). All modes are MSB first and operate with data of 16
to 32 bits.
Figure 6. Left-Justified Audio Input Mode
Figure 7. Right-Justified Audio Input Mode
ADCLRC/
DACLRC
CODEC_BCLK
ADCDAT/
DACDAT
1234
N
X
N
12
LEFT CHANNEL
3
RIGHT CHANNEL
1/
fS
X = DON’T CARE.
ADCLRC/
DACLRC
CODEC_BCLK
ADCDAT/
DACDAT
LEFT CHANNEL
RIGHT CHANNEL
1/
fS
X = DON’T CARE.
XN
X
3
2
1
XXN
4
4321
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADSP-BF535PKB-350 | IC DSP CONTROLLER 16BIT 260 BGA |
| ADSP-BF538BBCZ-4A | IC DSP CTLR 16BIT 316CSPBGA |
| ADSP-BF547YBCZ-4A | IC DSP BLACKFIN 400MHZ 400CSPBGA |
| ADSP-BF592BCPZ | IC DSP CTRLR 64LFCSP |
| ADSP-TS101SAB1-100 | IC DSP CTRLR 128BIT BUS 625BGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-BF526KBCZ4C2X | 制造商:Analog Devices 功能描述:DSP 32-BIT 400MHZ - Trays |
| ADSP-BF526KBCZ-4X | 制造商:Analog Devices 功能描述:LOW POWER BLACKFIN PROCESSOR WITH ADVANCED PERIPHERALS AND L - Trays |
| ADSP-BF526KBCZENGA | 制造商:Analog Devices 功能描述:LOW POWER BLACKFIN PROCESSOR WITH ADVANCED PERIPHERALS AND L - Trays |
| ADSP-BF526KBCZENGC2 | 制造商:Analog Devices 功能描述: |
| ADSP-BF526XKBCZ-4X | 制造商:Analog Devices 功能描述:LOW POWER BLACKFIN PROCESSOR WITH ADVANCED PERIPHERALS - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。