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參數(shù)資料
型號： ADS62C17IRGCT
廠商： Texas Instruments
文件頁數(shù)： 67/68頁
文件大小： 0K
描述： IC ADC 11BIT DUAL 200MSPS 64VQFN
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 11
采樣率（每秒）： 200M
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 1.1W
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 64-VQFN 裸露焊盤（9x9）
包裝： 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類型： 2 個差分，單極
產(chǎn)品目錄頁面： 888 (CN2011-ZH PDF)
其它名稱： 296-24232-6
DIGITAL CHARACTERISTICS — ADS62C17
GND
Logic0
V
=-350mV*
ODL
Logic1
V
=+350mV*
ODH
VOCM
DAnP /DBnP
DAnM/DBnM
*Withexternal100
termination
W
SLAS631A – APRIL 2009 – REVISED JULY 2009 ............................................................................................................................................................. www.ti.com
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1. AVDD = 3.3V, DRVDD = 1.8V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS – CTRL1, CTRL2, CTRL3, RESET, SCLK, SDATA, SEN (1)
High-level input voltage
1.3
All digital inputs support 1.8 V and 3.3 V CMOS
V
logic levels.
Low-level input voltage
0.4
SDATA, SCLK(2)
VHIGH = 3.3 V
16
High-level input current
A
SEN(3)
VHIGH = 3.3 V
10
SDATA, SCLK
VLOW = 0 V
0
Low-level input current
A
SEN
VLOW = 0 V
–20
Input capacitance
4
pF
DIGITAL OUTPUTS – CMOS INTERFACE (DA0-DA10, DB0-DB10, CLKOUT, SDOUT)
Ioh = 1mA
DRVDD – DRVDD
High-level output voltage
V
0.1
Low-level output voltage
Iol = 1mA
0
0.1
V
Output capacitance (internal to device)
2
pF
DIGITAL OUTPUTS – LVDS INTERFACE (DA0P/M TO DA10P/M, DB0P/M TO DB10P/M, CLKOUTP/M)
VODH, High-level output differential voltage
With external 100
termination
+275
+350
+425
mV
VODL, Low-level output differential voltage
With external 100
termination.
–425
–350
–275
mV
VOCM, Output common-mode voltage
1.0
1.15
1.40
V
Capacitance inside the device from each output
2
pF
Output Capacitance
to ground
(1)
SCLK, SDATA, SEN function as digital input pins in serial configuration mode.
(2)
SDATA, SCLK have internal 200 k
Ω pull-down resistor
(3)
SEN has internal 100 k
pull-up resistor to AVDD.
Figure 2. LVDS Output Voltage Levels
8
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS62C17
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