參數(shù)資料
型號(hào): ADS62C17IRGCT
廠商: Texas Instruments
文件頁(yè)數(shù): 53/68頁(yè)
文件大?。?/td> 0K
描述: IC ADC 11BIT DUAL 200MSPS 64VQFN
標(biāo)準(zhǔn)包裝: 1
位數(shù): 11
采樣率(每秒): 200M
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 1.1W
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 64-VQFN 裸露焊盤(pán)(9x9)
包裝: 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類(lèi)型: 2 個(gè)差分,單極
產(chǎn)品目錄頁(yè)面: 888 (CN2011-ZH PDF)
其它名稱(chēng): 296-24232-6
DA0
DA1
DA2
DA8
Pins
DA9
DA10
CLKOUT
11 bit ADC data
Channel A
SDOUT
11 bit ADC data
Channel B
DB0
DB1
DB2
DB8
DB9
DB10
CMOS Interface Power Dissipation
www.ti.com ............................................................................................................................................................. SLAS631A – APRIL 2009 – REVISED JULY 2009
Figure 60. Parallel CMOS Outputs
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every
output pin. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock
cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined
by the average number of output bits switching, which is a function of the sampling frequency and the nature of
the analog input signal.
Digital current due to CMOS output switching = CL × DRVDD × (N × FAVG),
where CL = load capacitance, N × FAVG = average number of output bits switching.
Figure 38 shows the current with various load capacitances across sampling frequencies at 2 MHz analog input
frequency.
Copyright 2009, Texas Instruments Incorporated
57
Product Folder Link(s): ADS62C17
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