參數(shù)資料
型號(hào): ADS5270
英文描述: 8-Channel, 12-Bit, 40MSPS ADC with Serial LVDS Interface
中文描述: 8通道,12位,40MSPS的ADC的串行LVDS接口
文件頁數(shù): 9/18頁
文件大小: 439K
代理商: ADS5270
"#$%&
SBAS293D JANUARY 2004 REVISED MAY 2004
www.ti.com
9
PIN DESCRIPTIONS
NAME
PIN #
NUMBER
OF PINS
9
14
2
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I/O
DESCRIPTION
AVDD
AVSS
LVDD
LVSS
IN1P
IN1N
IN2P
IN2N
IN3P
IN3N
IN4P
IN4N
IN5P
IN5N
IN6P
IN6N
IN7P
IN7N
IN8P
IN8N
REFT
REFB
VCM
INT/EXT
PD
LCLKP
LCLKN
ADCLK
OUT1P
OUT1N
OUT2P
OUT2N
OUT3P
OUT3N
OUT4P
OUT4N
OUT5P
OUT5N
OUT6P
OUT6N
OUT7P
OUT7N
OUT8P
OUT8N
ADCLKP
ADCLKN
ISET
RESET
CS
SDA
SCLK
1, 7, 14, 47, 54, 60, 63, 70, 75
4, 8, 11, 50, 53, 57, 61, 62, 68, 72-74, 79, 80
25, 35
15, 17, 18, 26, 36, 43, 44, 46
2
3
5
6
9
10
12
13
48
49
51
52
55
56
58
59
67
66
65
69
16
19
20
71
21
22
23
24
27
28
29
30
31
32
33
34
37
38
39
40
41
42
64
45
76
77
78
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Analog Power Supply
Analog Ground
LVDS Power Supply
LVDS Ground
Channel 1 Differential Analog Input High
Channel 1 Differential Analog Input Low
Channel 2 Differential Analog Input High
Channel 2 Differential Analog Input Low
Channel 3 Differential Analog Input High
Channel 3 Differential Analog Input Low
Channel 4 Differential Analog Input High
Channel 4 Differential Analog Input Low
Channel 5 Differential Analog Input High
Channel 5 Differential Analog Input Low
Channel 6 Differential Analog Input High
Channel 6 Differential Analog Input Low
Channel 7 Differential Analog Input High
Channel 7 Differential Analog Input Low
Channel 8 Differential Analog Input High
Channel 8 Differential Analog Input Low
Reference Top Voltage (0.1
μ
F capacitor to ground)
Reference Bottom Voltage (0.1
μ
F capacitor to ground)
Common-Mode Output Voltage
Internal/External Reference Select; 0 = External, 1 = Internal
Power-Down; 0 = Normal, 1 = Power-Down
Positive LVDS Clock
Negative LVDS Clock
Data Converter Clock Input
Channel 1 Positive LVDS Data Output
Channel 1 Negative LVDS Data Output
Channel 2 Positive LVDS Data Output
Channel 2 Negative LVDS Data Output
Channel 3 Positive LVDS Data Output
Channel 3 Negative LVDS Data Output
Channel 4 Positive LVDS Data Output
Channel 4 Negative LVDS Data Output
Channel 5 Positive LVDS Data Output
Channel 5 Negative LVDS Data Output
Channel 6 Positive LVDS Data Output
Channel 6 Negative LVDS Data Output
Channel 7 Positive LVDS Data Output
Channel 7 Negative LVDS Data Output
Channel 8 Positive LVDS Data Output
Channel 8 Negative LVDS Data Output
Positive LVDS ADC Clock Output
Negative LVDS ADC Clock Output
Bias Current Setting Resistor of 56k
to Ground
Reset to Default; 0 = Reset, 1 = Normal
Chip Select; 0 = Select, 1 = No Select
Serial Data Input
Serial Data Clock
I/O
I/O
O
I
I
O
O
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I/O
I
I
I
I
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