參數(shù)資料
型號： ADS5270
英文描述： 8-Channel, 12-Bit, 40MSPS ADC with Serial LVDS Interface
中文描述： 8通道，12位，40MSPS的ADC的串行LVDS接口
文件頁數(shù)： 4/18頁
文件大小： 439K
代理商： ADS5270
"#$%&
SBAS293D JANUARY 2004 REVISED MAY 2004
www.ti.com
4
AC CHARACTERISTICS
TMIN = 40
°
C, TMAX = +85
°
C. Typical values are at TA = 25
°
C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V,
1dBFS, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
ADS5270
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC CHARACTERISTICS
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
f1 = 9.5MHz at 7dBFS
f2 = 10.2MHz at 7dBFS
fIN = 5MHz
Signal Applied to 7 Channels;
Measurement Taken on the Channel with
No Input Signal
89
87
85
83
95
95
90
87
89
87
85
83
70.5
70.5
70.5
70.5
70
70
70
70
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
SFDR
Spurious-Free Dynamic Range
78
HD2
2nd-Order Harmonic Distortion
85
HD3
3rd-Order Harmonic Distortion
78
SNR
Signal-to-Noise Ratio
68
SINAD
Signal-to-Noise and Distortion
67.5
IMD
Two-Tone Intermodulation Distortion
85
dBFS
ENOB
Effective Number of Bits
11.3
Bits
Crosstalk
90
dBc
LVDS DIGITAL DATA AND CLOCK OUTPUTS
Test conditions at IO = 3.5mA, RLOAD = 100
, and CLOAD = 9pF. IO refers to the current setting for the LVDS buffer. RLOAD is the differential load resistance
between the differential LVDS pair. CLOAD is the effective single-ended load capacitance between the differential LVDS pins and ground. CLOAD includes the
receiver input parasitics as well as the routing parasitics. Measurements are done with a transmission line of 100
differential impedance between the device and
the load. All LVDS specifications are functionally tested, but not parametrically tested.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DC SPECIFICATIONS(1)
VOH
VOL
VOD
VOS
CO
VOD
VOS
ISOUT
ISOUTNP
DRIVER AC SPECIFICATIONS
Clock
Clock Signal Duty Cycle
Minimum Data Setup TIme(4, 5)
Minimum Data Hold Time(4, 5)
tRISE/tFALL
VOD Rise Time or VOD Fall Time
Output Voltage High, OUTP or OUTN
Output Voltage Low, OUTP or OUTN
Output Differential Voltage,
OUTP OUTN
Output Offset Voltage(2)
Output Capacitance(3)
Change in
VOD
Between 0 and 1
Change Between 0 and 1
Output Short-Circuit Current
Output Current
RLOAD = 100
±
1%; See LVDS Timing Diagram, Page 7
RLOAD = 100
±
1%
RLOAD = 100
±
1%
RLOAD = 100
±
1%; See LVDS Timing Diagram, Page 7
VCM = 1.5V
RLOAD = 100
±
1%
RLOAD = 100
±
1%
Drivers Shorted to Ground
Drivers Shorted Together
1375
1025
350
1200
4
1500
mV
mV
mV
mV
pF
mV
mV
mA
mA
900
300
1100
400
1300
25
25
40
12
6
×
ADCLK
45
50
650
650
400
250
200
150
55
%
ps
ps
IO = 2.5mA
IO = 3.5mA
IO = 4.5mA
IO = 6mA
ps
ps
ps
(1)The DC specifications refer to the condition where the LVDS outputs are not switching, but are permanently at a valid logic level 0 or 1.
(2)VOS refers to the common-mode of OUTP and OUTN.
(3)Output capacitance inside the device, from either OUTP or OUTN to ground.
(4)Refer to the LVDS application note (SBAA118) for a description of data setup and hold times.
(5)Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume that the data and clock
paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as reduced timing margins.
相關(guān)PDF資料
PDF描述
ADS5270IPFP 8-Channel, 12-Bit, 40MSPS ADC with Serial LVDS Interface
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