參數(shù)資料
型號: ADS5270
英文描述: 8-Channel, 12-Bit, 40MSPS ADC with Serial LVDS Interface
中文描述: 8通道,12位,40MSPS的ADC的串行LVDS接口
文件頁數(shù): 6/18頁
文件大小: 439K
代理商: ADS5270
"#$%&
SBAS293D JANUARY 2004 REVISED MAY 2004
www.ti.com
6
SERIAL INTERFACE TIMING
ADDRESS
DATA
DESCRIPTION
REMARKS
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
0. LVDS BUFFERS
Normal ADC Output
Deskew Pattern
Sync Pattern
Custom Pattern
Output Current in LVDS = 3.5mA
Output Current in LVDS = 2.5mA
Output Current in LVDS = 4.5mA
Output Current in LVDS = 6.0mA
1. LSB/MSB MODE
Default LVDS Clock Output Current
2X LVDS Clock Output Current
LSB Mode
MSB Mode
2. POWER-DOWN ADC CHANNELS
0
0
1
1
0
1
0
1
Patterns Get Reversed in MSB First
Mode of LVDS
0
0
1
1
0
1
0
1
0
0
0
1
D3
0
0
0
D2
X
0
1
D1
X
X
X
D0
1
X
X
0
0
1
0
D3
D2
D1
D0
X
X
X
X
Power-Down Channels 1 to 4; D3 is
for Channel 4 and D0 for Channel 1
Example: 1010 Powers Down
Channels 4 and 2 and Keeps
Channels 1 and 3 Alive
0
0
1
1
3. POWER-DOWN ADC CHANNELS
D3
D2
D1
D0
X
X
X
X
Power-Down Channels 5 to 8; D3 is
for Channel 8 and D0 for Channel 5
CUSTOM PATTERN (registers 4-6)
D3
MSB
X
X
D2
X
X
X
D1
X
X
X
D0
X
X
LSB
0
0
0
1
1
1
0
0
1
0
1
0
Bits for Custom Pattern
TEST PATTERNS(1)
Deskew
Sync
Custom
101010101010
000000111111
Any 12-bit pattern that is defined in the custom pattern registers 4 to 6. The output comes out in the following order:
D0(4) D1(4) D2(4) D3(4) D0(5) D1(5) D2(5) D3(5) D0(6) D1(6) D2(6) D3(6)
where, for example, D0(4) refers to the D0 bit of register 4, etc.
(1)Default is LSB first. If MSB is selected the above patterns will be reversed.
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