參數(shù)資料
型號(hào): ADS1271IPWR
元件分類(lèi): ADC
英文描述: 24 BIT WIDE BANDWIDTH ANALOG TO DIGITAL CONVERTER
中文描述: 24位寬帶模數(shù)轉(zhuǎn)換器
文件頁(yè)數(shù): 3/29頁(yè)
文件大小: 381K
代理商: ADS1271IPWR
SBAS306A NOVEMBER 2004 REVISED DECEMBER 2004
www.ti.com
3
ELECTRICAL CHARACTERISTICS
All specifications at TA = 40
°
C to +105
°
C, AVDD = +5V, DVDD = +1.8V, fCLK = 27MHz, and VREF = +2.5V, unless otherwise noted.
ADS1271
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Analog Inputs
Full-scale input voltage (FSR)(1)
Absolute input voltage
Common-mode input voltage
VIN = (AINP – AINN)
AINP or AINN to AGND
VCM = (AINP + AINN)/2
±
VREF
V
V
V
k
k
k
AGND – 0.1
AVDD + 0.1
2.5
16.4
16.4
32.8
Differential input
impedance
High-Speed mode
High-Resolution mode
Low-Power mode
DC Performance
Resolution
No missing codes
24
Bits
SPS
SPS
SPS
High-Speed mode
High-Resolution mode
Low-Power mode
105,469
52,734
52,734
±
0.0006
0.150
On the level of the noise
1.8
0.1
2
9.0
6.5
9.0
100
80
80
Data rate (fDATA)
Integral nonlinearity (INL)
Differential input, VCM = 2.5V
Without calibration
With calibration
±
0.0015
% of FSR(1)
mV
Offset error
High-Speed mode
1
Offset drift
Gain error
Gain error drift
μ
V/ C
%
ppm/
°
C
μ
V, rms
μ
V, rms
μ
V, rms
dB
dB
dB
0.5
High-Speed mode
High-Resolution mode
Low-Power mode
Shorted input
20
Noise
Common-mode rejection
fCM = 60Hz
90
Power-supply
rejection
AC Performance
AVDD
DVDD
f = 60Hz
Signal-to-noise ratio
(SNR) (2)
(unweighted)
Total harmonic distortion
(THD) (3)
Spurious free dynamic range
Passband ripple
Passband
3dB Bandwidth
Stop band attenuation
High-Speed mode
High-Resolution mode
Low-Power mode
99
106
109
106
105
108
dB
dB
dB
dB
dB
dB
Hz
Hz
dB
Hz
Hz
Hz
VIN = 1kHz, 0.5dBFS
95
±
0.005
0.453 fDATA
0.49 fDATA
100
High-Speed mode
High-Resolution mode
Low-Power mode
High-Speed and
Low-Power modes
High-Resolution mode
High-Speed and
Low-Power modes
High-Resolution mode
0.547 fDATA
0.547 fDATA
0.547 fDATA
63.453 fDATA
127.453 fDATA
63.453 fDATA
Stop band
Group delay
38/fDATA
s
39/fDATA
s
Settling time (latency)
Complete settling
76/fDATA
s
Complete settling
78/fDATA
s
(1)FSR = full-scale range = 2VREF.
(2)Minimum SNR is ensured by the limit of the
DC noise
specification.
(3)THD includes the first nine harmonics of the input signals.
(4)MODE and FORMAT pins excluded.
(5)See the text for more details on SCLK.
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