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參數(shù)資料
| 型號： | ADS1271IPWR |
| 元件分類： | ADC |
| 英文描述： | 24 BIT WIDE BANDWIDTH ANALOG TO DIGITAL CONVERTER |
| 中文描述： | 24位寬帶模數(shù)轉(zhuǎn)換器 |
| 文件頁數(shù)： | 18/29頁 |
| 文件大小： | 381K |
| 代理商： | ADS1271IPWR |
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SBAS306A NOVEMBER 2004 REVISED DECEMBER 2004
www.ti.com
18
SYNCHRONIZATION
The SYNC/PDWN pin has two functions. When pulsed, it
synchronizes the start of conversions and, if held low for
more than 2
19
CLK cycles (t
SYN
), places the ADS1271 in
Power-Down mode. See the
Power-Down and Offset
Calibration
section for more details.
The ADS1271 can be synchronized by taking
SYNC/PDWN low. This stops the conversion process and
resets the internal counters used by the digital filter. Return
SYNC/PDWN high on the rising edge of CLK to begin the
conversion
process.
Synchronization
conversions to be aligned with an external event; for
example, the changing of an external multiplexer on the
analog inputs. It can also be used to synchronize the
conversions of multiple ADS1271s.
allows
the
In the SPI format, DRDY goes high as soon as
SYNC/PDWN is taken low, as shown in Figure 44. After
SYNC/PDWN is returned high, DRDY stays high while the
digital filter is settling. Once valid data is ready for retrieval,
DRDY goes low.
In the Frame-Sync format, DOUT goes low as soon as
SYNC/PDWN is taken low, as shown in Figure 45. After
SYNC/PDWN is returned high, DOUT stays low while the
digital filter is settling. Once valid data is ready for retrieval,
DOUT begins to output valid data. The device detects the
state of the SYNC/PDWN pin on the falling edge. When
synchronizing multiple devices, set the SYNC/PDWN pin
high on the rising edge of SCLK to ensure all devices are
restarted on the same SCLK period. It is recommended to
leave
FSYNC
and
SCLK
synchronization.
running
during
a
CLK
DRDY
SYNC/PDWN
t
NDR
t
SYN
SYMBOL
t
SYN
Synchronize pulse width
2
18
1
CLK periods
t
NDR
Time for new data to be ready
128
Conversions
(1/f
DATA
)
MIN
TYP
MAX
UNITS
DESCRIPTION
Figure 44. Synchronization Timing for SPI format
CLK
FSYNC
Valid Data
DOUT
SYNC/PDWN
t
NDR
t
SYN
SYMBOL
t
SYN
Synchronize pulse width
2
18
1
CLK periods
t
NDR
Time for new data to be ready
128
Conversions
(1/f
DATA
)
MIN
TYP
MAX
UNITS
DESCRIPTION
129
Figure 45. Synchronization Timing for Frame-Sync Format
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| ADS1271IPWRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-Bit 105kSPS Ind Delta-Sigma RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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| ADS1274EVM | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS1274EVM Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| ADS1274EVM-PDK | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS1274EVM-PDK Demo Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| ADS1274IPAPR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Quad 128kHz Simul 24B Delta Sigma ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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