參數(shù)資料
型號(hào): ADS1271IPWR
元件分類: ADC
英文描述: 24 BIT WIDE BANDWIDTH ANALOG TO DIGITAL CONVERTER
中文描述: 24位寬帶模數(shù)轉(zhuǎn)換器
文件頁(yè)數(shù): 16/29頁(yè)
文件大?。?/td> 381K
代理商: ADS1271IPWR
SBAS306A NOVEMBER 2004 REVISED DECEMBER 2004
www.ti.com
16
VOLTAGE REFERENCE INPUTS (VREFP,
VREFN)
The voltage reference for the ADS1271 ADC is the
differential voltage between VREFP and VREFN:
V
REF
= (VREFPVREFN). The reference inputs use a
structure similar to that of the analog inputs with the
equivalent circuitry on the reference inputs shown in
Figure 41. As with the analog inputs, the load presented by
the switched capacitor can be modeled with an effective
impedance, as shown in Figure 42.
ESD
Protection
AVDD
AVDD
VREFN
VREFP
Figure 41. Equivalent Reference Input Circuitry
VREFP
VREFN
Zeff = 4.2k
×
(6.75MHz/f
MOD
)
Figure 42. Effective Reference Impedance
ESD diodes protect the reference inputs. To keep these
diodes from turning on, make sure the voltages on the
reference pins do not go below AGND by more than 0.1V,
and likewise do not exceed AVDD by 0.1V:
0.1V < (VREFP or VREFN) < AVDD + 0.1V
A high-quality reference voltage with the appropriate drive
strength is essential for achieving the best performance from
the ADS1271. Noise and drift on the reference degrade
overall system performance. See the
Application
Information
section for example reference circuits.
CLOCK INPUT (CLK)
The ADS1271 requires an external clock signal to be
applied to the CLK input pin. As with any high-speed data
converter, a high-quality, low-jitter clock is essential for
optimum performance. Crystal clock oscillators are the
recommended clock source. Make sure to avoid excess
ringing on the clock input; keeping the clock trace as short
as possible using a 47
series resistor will help.
The ratio between the clock frequency and output data rate
is a function of the mode and format. Table 3 shows the
ratios when the SPI format is selected. Also included in this
table is the typical CLK frequency and the corresponding
data rate. When High-Speed mode is used, each
conversion
takes
256
High-Resolution or Low-Power modes are selected, the
conversions take 512 CLK periods.
CLK
periods.
When
Table 4 shows the ratios when the Frame-Sync format is
selected. When using the Frame-Sync format in either
High-Resolution or Low-Power mode, the f
CLK
/f
DATA
ratio
can be 256 or 512. The ADS1271 automatically detects
which ratio is being used. Using a ratio of 512 allows the
CLK frequency to be reduced by a factor of two while
maintaining the same data rate. The output data rate
scales with the clock frequency. See the
Serial Interface
section for more details on the Frame-Sync operation.
Table 3. Clock Ratios for SPI Format
MODE SELECTION
High-Speed
fCLK/fDATA
256
TYPICAL fCLK (MHz)
CORRESPONDING DATA RATE (SPS)
105,469
27
High-Resolution
512
27
52,734
Low-Power
512
27
52,734
Table 4. Clock Ratios for Frame-Sync Format
MODE SELECTION
High-Speed
fCLK/fFRAME
256
TYPICAL fCLK (MHz)
CORRESPONDING DATA RATE (SPS)
105,469
27
High-Resolution
256
13.5
52,734
512
27
52,734
Low-Power
256
13.5
52,734
512
27
52,734
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