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參數(shù)資料
| 型號(hào)： | ADS1271IPWR |
| 元件分類： | ADC |
| 英文描述： | 24 BIT WIDE BANDWIDTH ANALOG TO DIGITAL CONVERTER |
| 中文描述： | 24位寬帶模數(shù)轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 15/29頁(yè) |
| 文件大?。?/td> | 381K |
| 代理商： | ADS1271IPWR |
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SBAS306A NOVEMBER 2004 REVISED DECEMBER 2004
www.ti.com
15
ANALOG INPUTS (AINP, AINN)
The ADS1271 measures the differential input signal
V
IN
= (AINP – AINN) against the differential reference
V
REF
= (VREFP – VREFN). The most positive measurable
differential input is +V
REF
, which produces the most
positive digital output code of 7FFFFFh. Likewise, the
most negative measurable differential input is V
REF
,
which produces the most negative digital output code of
800000h.
While the ADS1271 measures the differential input signal,
the absolute input voltage is also important. This is the
voltage on either input (AINP or AINN) with respect to
AGND. The range for this voltage is:
0.1V < (AINN or AINP) < AVDD +0.1V
If either input is taken below –0.1V or above (AVDD + 0.1),
ESD protection diodes on the inputs may turn on.
The ADS1271 uses switched-capacitor circuitry to
measure the input voltage. Internal capacitors are charged
by the inputs and then discharged. Figure 38 shows a
conceptual diagram of these circuits. Switch S2
represents the net effect of the modulator circuitry in
discharging
the
sampling
implementation is different. The timing for switches S1 and
S2 is shown in Figure 39. The sampling time (t
SAMPLE
) is
the inverse of modulator sampling frequency (f
MOD
) and is
a function of the mode, format, and frequency of CLK, as
shown in Table 2. When using the Frame-Sync format with
High-Resolution or Low-Power modes, the ratio between
f
MOD
and f
CLK
depends on the frame period that is set by
the FSYNC input.
capacitor;
the
actual
ESD Protection
AVDD
AGND
AVDD
AINP
9pF
AINN
AGND
S
1
S
1
S
2
Figure 38. Equivalent Analog Input Circuitry
ON
OFF
S1
ON
OFF
S2
t
SAMPLE
= 1/f
MOD
Figure 39. S1 and S2 Switch Timing for Figure 38
Table 2. Modulator Frequency for the Different
Mode and Format Settings
MODE
INTERFACE
FORMAT
fMOD
fCLK/4
fCLK/4
High-Speed
SPI or Frame-Sync
High-Resolution
SPI
Frame-Sync
fCLK/4 or fCLK/2
fCLK/8
fCLK/8 or fCLK/4
Low-Power
SPI
Frame-Sync
The average load presented by the switched capacitor
input can be modeled with an effective differential
impedance, as shown in Figure 40. Note that the effective
impedance is a function of f
MOD
.
AINP
AINN
Zeff = 16.4k
×
(6.75MHz/f
MOD
)
Figure 40. Effective Input Impedances
The ADS1271 is a very high-performance ADC. For
optimum performance, it is critical that the appropriate
circuitry be used to drive the ADS1271 inputs. See the
Application Information
section for the recommended
circuits.
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| ADS1271IPWRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-Bit 105kSPS Ind Delta-Sigma RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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| ADS1274EVM-PDK | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS1274EVM-PDK Demo Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| ADS1274IPAPR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Quad 128kHz Simul 24B Delta Sigma ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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