參數(shù)資料
型號(hào)： ADS1259IPW
廠(chǎng)商： Texas Instruments
文件頁(yè)數(shù)： 7/48頁(yè)
文件大?。?/td> 0K
描述： IC ADC 24BIT 14KSPS LN 20TSSOP
產(chǎn)品培訓(xùn)模塊： Industrial Automation Overview
標(biāo)準(zhǔn)包裝： 70
位數(shù)： 24
采樣率（每秒）： 14k
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 管件
輸入數(shù)目和類(lèi)型： 2 個(gè)單端，單極；2 個(gè)單端，雙極；1 個(gè)差分，單極；1 個(gè)差分，雙極
其它名稱(chēng)： 296-27184-5
t
SAMPLE
MOD
=1/f
ON
OFF
S
1
S
2
OFF
ON
S
1
S
1
AVSS+2.5V
R
=R
||2R
=120k
R
=R
=500k
W
COM
EFFA
DIFF
EFFB
EFFA
AVSS+2.5V
R
=500kW
EFFA
R
=130kW
EFFB
(f
=0.9216MHz)
MOD
R
=500kW
EFFA
AINN
AINP
C
=2pF
A1
C =8pF
B
C
=2pF
A2
S
2
AVSS+2.5V
S
2
AVSS+2.5V
AINN
AINP
Equivalent
Circuit
AVDD
AVSS
R
=
EFF
f
C
MOD
X
1
ESDDiodes
andf
=f
/8
CLK
MOD
SBAS424D
– JUNE 2009 – REVISED AUGUST 2011
ANALOG INPUTS (AINP, AINN)
ESD diodes protect the analog inputs. To keep these
diodes from turning on, make sure the voltages on
The ADS1259 measures the differential input signal
the input pins do not go below AVSS by more than
VIN = (AINP – AINN) against the differential reference
300mV, and likewise do not exceed AVDD by more
VREF = (VREFP – VREFN) using internal capacitors
than 300mV.
that
are
continuously
charged
and
discharged.
Figure 37 shows the simplified schematic of the ADC
AVSS
– 300mV < (AINP or AINN) < AVDD + 300mV.
input circuitry; the right side of the figure illustrates
Note that the valid input range is:
the input circuitry with the capacitors and switches
replaced
by
an
equivalent
circuit.
AVSS
– 100mV < (AINP or AINN) < AVDD + 100mV
demonstrates the ON/OFF timings for the switches of
In Figure 37, S1 switches close during the input
sampling phase. With switch S1 closed, CA1 charges
to AINP, CA2 charges to AINN, and CB charges to
(AINP
– AINN). For the discharge phase, S1 opens
first and then S2 closes. CA1 and CA2 discharge to
approximately to AVSS + 2.5V and CB discharges to
0V. This two-phase sample/discharge cycle repeats
Figure 36. S1 and S2 Switch Timing for Figure 37
with a period of tSAMPLE = 1/fMOD. fMOD is the operating
frequency of the modulator, where fMOD = fCLK/8.
Although
optimized
for
differential
signals,
the
The charging of the input sampling capacitors draws
ADS1259 inputs may be driven with a single-ended
a transient current from the source driving the
signal by fixing one input to AVSS or mid-supply. Full
ADS1259 ADC inputs. The average value of this
dynamic range is achieved when the inputs are
current can be used to calculate an effective
differentially driven
±VREF.
impedance (REFF) where REFF = VIN/IAVERAGE. These
impedances scale inversely with fMOD. For example, if
As a result of the switched-capacitor input structure of
fMOD is reduced by a factor of two, the impedances
the ADS1259, a buffer is recommended to drive the
double. Note that the sampling capacitors can vary
analog inputs. An input filter comprised of 20
to 50Ω
±15% over production lots and typically vary 1% with
resistors and 10nF capacitors should be used
temperature.
The
variations
of
the
sampling
between the buffer and the ADS1259 inputs.
capacitors have a corresponding effect on the analog
input impedance.
Figure 37. Simplified ADC Input Structure
Copyright
2009–2011, Texas Instruments Incorporated
15
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ADS-126 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:
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