Minimum/maximum specifications are at T
參數(shù)資料
型號： ADS1259IPW
廠商： Texas Instruments
文件頁數(shù)： 23/48頁
文件大小： 0K
描述： IC ADC 24BIT 14KSPS LN 20TSSOP
產(chǎn)品培訓(xùn)模塊： Industrial Automation Overview
標(biāo)準(zhǔn)包裝： 70
位數(shù)： 24
采樣率（每秒）： 14k
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 管件
輸入數(shù)目和類型： 2 個單端，單極；2 個單端，雙極；1 個差分，單極；1 個差分，雙極
其它名稱： 296-27184-5
SBAS424D
– JUNE 2009 – REVISED AUGUST 2011
ELECTRICAL CHARACTERISTICS
Minimum/maximum specifications are at TA = –40°C to +105°C. Typical specifications are at TA = +25°C, AVDD = +2.5V, AVSS = –2.5V,
DVDD = +3.3V, fCLK = 7.3728MHz, VREF = 2.5V, and fDATA = 60SPS, unless otherwise noted.
ADS1259
ADS1259B
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Full-scale input voltage range (FSR)
VIN = (AINP – AINN)
±VREF
V
Absolute input voltage
AVSS
– 0.1
AVDD + 0.1
AVSS
– 0.1
AVDD + 0.1
V
(AINP, AINN to DGND)
Differential input impedance
120
k
Common-mode input impedance
500
k
Ω
SYSTEM PERFORMANCE
Resolution
No missing codes
24
Bits
Data rate (fDATA)
10
14400
10
14400
SPS
(1)
Integral nonlinearity
Best fit method
±0.0003
±0.001
±0.00004
(2)
±0.0003
%FSR
Offset error
±40
±250
±40
±250
μV
Offset error after calibration
(3)
±1
μV
Offset drift
(4)
TA = –40°C to +105°C
0.05
0.25
0.05
0.25
μV/°C
Gain error
(5)
±0.05
±0.5
±0.05
±0.5
%
Gain error after calibration
(3)
±0.0002
%
Gain drift
(4)
TA = –40°C to +105°C
0.5
2.5
0.5
2.5
ppm/
°C
Normal mode rejection
Common-mode rejection
60Hz, ac
(6)
100
120
100
120
dB
Noise
0.7
μV
AVDD, AVSS power-supply
60Hz, ac
(6)
85
95
85
95
dB
rejection
DVDD power-supply rejection
60Hz, ac
(6)
85
110
85
110
dB
OUT-OF-RANGE DETECTION
Level
±105
%FSR
Threshold
(7)
Accuracy
±0.5
%FSR
VOLTAGE REFERENCE INPUTS
VREF = (VREFP –
AVDD
– AVSS +
AVDD
– AVSS +
Reference input range (VREF)
0.5
2.5
0.5
2.5
V
VREFN)
200mV
Negative reference absolute input
AVSS
–
AVSS
–
VREFP
– 0.5
VREFP
– 0.5
V
(VREFN to DGND)
100mV
Positive reference absolute input
VREFN + 0.5
AVDD + 100mV
VREFN + 0.5
AVDD + 100mV
V
(VREFP to DGND)
200nA +
Average reference input current
(8)
60nA/V
Average reference input current drift
Internal or external clock
0.2
nA/
°C
INTERNAL VOLTAGE REFERENCE
VREFOUT = (REFOUT –
Reference output voltage
2.5
V
AVSS)
Accuracy
TA = +25°C
±0.4
±0.2
%
TA = –40°C to +105°C
10
40
4
12
ppm/
°C
Temperature drift
(4)
TA = 0°C to +85°C
2
5
ppm/
°C
Drive current sink and source
–10
10
–10
10
mA
(9)
Load regulation
10
μV/mA
Turn-on settling time
(10)
±0.001% settling
1
s
Long-term stability
0 to 1000 hours
70
ppm/1000hr
Thermal hysteresis
(11)
30
ppm
(1)
SPS = samples per second.
(2)
Shaded cells indicate improved specifications of the ADS1259B.
(3)
Calibration accuracy is on the level of noise (signal and ADC), reduced by the effect of 16 reading averaging.
(4)
Reference drift specified by design and final production test. Drift calculated over the specified temperature range using box method.
(5)
Excludes internal reference error.
(6)
fDATA = 14.4kSPS. Placing a notch of the digital filter at 60Hz (setting fDATA = 10SPS or 60SPS) further improves the common-mode
rejection and power-supply rejection of this input frequency.
(7)
Absolute input voltage range for out-of-range specification: AVSS + 150mV
≤ AINP or AINN ≤ AVDD – 150mV.
(8)
Over the range: AVSS
≤ VREFP or VREFN ≤ AVDD. For reference voltage exceeding AVDD or AVSS, input current = 150nA/10mV.
(9)
Limit the reference output current to
±10mA.
(10) CREFOUT = 1μF, CREFIN = 1μF.
(11) See the Thermal Hysteresis section.
Copyright
2009–2011, Texas Instruments Incorporated
3
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