參數(shù)資料
型號(hào)： ADS1250
英文描述： 20-Bit Data Acquisition System ANALOG-TO-DIGITAL CONVERTER
中文描述： 20位數(shù)據(jù)采集系統(tǒng)的模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù)： 15/20頁(yè)
文件大?。?/td> 196K
代理商： ADS1250
15
ADS1250
19
OUT
LSB
DOUT
SCLK
CS
DRDY
CLK
20
21
22
23
24
t
5
t
6
t
12
t
7
1
2
OUT
MSB
t
9
t
10
t
11
t
8
FIGURE 18. Method 2: Four-Wire Interface Using a Free-Running SCLK.
Method 2: Four-Wire Interface
The second method of receiving data also uses a simple
four-wire interface (CS, SCLK, DOUT, and DRDY). The
main difference from method 1 is that SCLK is a free-
running clock. The DRDY line will pulse LOW for the time
defined by t
2
after the DOR is updated. The processor would
then take CS LOW to select the device for communication.
The recommended method of using CS is to take CS LOW
on the falling edge of SCLK. The only timing constraint of
CS is that the setup time (t
9
) for the data must be met before
the rising edge of SCLK. Once CS is taken LOW, the DOUT
would be driven to the level dictated by the MSB of the data
output register. CS would be held low for 20 (or 24) SCLKs
to read the contents of the DOR. The data bits in the DOR
are shifted out on the DOUT pin after the falling edge of
SCLK. If CS is held low for more than 20 SCLKs, the data
would be 0 padded. Taking CS HIGH will take DOUT to a
high-impedance state. The timing for the data transfer is
shown in Figure 18 (see Table III). A simple four-wire
interface is shown in Figure 19. The P1.0 output from the
8xC51 is a free-running clock.
FIGURE 19. Four-Wire Interface to an 8xC51 (Free-Running SCLK).
DV
DD
DV
DD
8xC51
P1.0 / T2
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
P3.0
P3.1
P3.2 / INT0
P3.3
P3.4
P3.5
P3.6
P3.7
XTAL2
XTAL1
V
SS
V
CC
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
EA
ALE
PSEN
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
DGND
C1
XTAL
C2
+V
IN
–V
IN
AGND
+V
S
V
REF
DSYNC
+V
D
DGND
DGND
G1
G0
CS
DRDY
CLK
SCLK
DOUT
DV
DD
V
Circuit
AGND
AV
DD
DGND
DGND
ADS1250
相關(guān)PDF資料
PDF描述
ADS1250U 20-Bit Data Acquisition System ANALOG-TO-DIGITAL CONVERTER
ADS1252 24-Bit, 40kHz ANALOG-TO-DIGITAL CONVERTER
ADS1252U 24-Bit, 40kHz ANALOG-TO-DIGITAL CONVERTER
ADS1252K5 24-Bit, 20kHz, Low-Power ANALOG-TO-DIGITAL CONVERTER
ADS1254 24-Bit, 20kHz, Low Power ANALOG-TO-DIGITAL CONVERTER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADS1250U 功能描述:模數(shù)轉(zhuǎn)換器 - ADC SpeedPlus 20-Bit Data Acq System RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS1250U/1K 功能描述:模數(shù)轉(zhuǎn)換器 - ADC SpeedPlus 20-Bit Data Acq System RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS1250U/1KG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC SpeedPlus 20-Bit Data Acq System RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS1250UG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC SpeedPlus 20-Bit Data Acq System RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS1251 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:24-Bit, 20kHz, Low-Power ANALOG-TO-DIGITAL CONVERTER
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