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參數(shù)資料
| 型號： | ADS1250 |
| 英文描述： | 20-Bit Data Acquisition System ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 20位數(shù)據(jù)采集系統(tǒng)的模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 196K |
| 代理商： | ADS1250 |
12
ADS1250
FIGURE 11. DSYNC to CLK Timing for Synchronizing
Multiple ADS1250s.
t
13
t
14
CLK
DSYNC
FIGURE 12. Exactly Synchronizing Multiple ADS1250s to an Asynchronous DSYNC Signal.
DSYNC
CLK
DGND
ADS1250
DOUT
SCLK
DV
DD
D
CLK
1/2 74AHC74
1/6 74AHC04
Q
Q
DSYNC
CLK
DGND
ADS1250
DOUT
SCLK
DV
DD
DSYNC
CLK
DGND
ADS1250
DOUT
SCLK
DV
DD
Asynchronous
DSYNC
Strobe
DGND
DV
DD
OSC
TABLE III. Digital Timing.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
DOR Write Time (Using CS)
DRDY LOW Time
DOR Write Time (CS HIGH)
DRDY HIGH Time
Rising Edge of CLK to Falling Edge of DRDY
Falling Edge of DRDY to Falling Edge of CS
Falling Edge of CS to Rising Edge of DRDY
Falling Edge of CS to Rising Edge of SCLK or
Falling Edge of DRDY to Rising Edge of SCLK if CS is Tied LOW
Falling Edge of CS to DOUT Valid or
Falling Edge of DRDY to DOUT Valid if CS is Tied LOW (Setup Time)
Falling Edge of SCLK to DOUT Valid (Hold Time)
Falling Edge of SCLK to Next DOUT Valid (Setup Time)
Rising Edge of CS to DOUT High Impedance
DSYNC Pulse Width
Falling Edge of CLK to Falling Edge of DSYNC
6 CLK
6 CLK
6 CLK
6 CLK
30
ns
ns
ns
ns
ns
ns
ns
30
6 CLK
30
ns
t
9
30
ns
ns
ns
ns
ns
ns
t
10
t
11
t
12
t
13
t
14
5
30
30
100
2
DSYNC
The DSYNC signal can be used is two ways. First, DSYNC
can be used to synchronize multiple converters. This is done
by applying a negative-going pulse on DSYNC. The nega-
tive pulse resets the current modulator count to zero and
places it in a hold state. The modulator is released from the
hold state and synchronization occurs on the rising edge of
DSYNC. DSYNC does not reset the internal data to zero.
Synchronization assumes that each ADS1250 is driven from
the same system clock. If the DSYNC pulse is completely
asynchronous to the master clock, some ADS1250s may
start-up one CLK clock cycle before the others.
Therefore, the output data will be synchronized, but only to
within one CLK clock cycle. To ensure exact synchroniza-
tion to the same CLK clock edge, the timing relationship
between the DSYNC and CLK signals must be observed, as
shown in Figure 11 and Table III. Figure 12 shows a simple
circuit which can be used to clock multiple ADS1250s from
one ADS1250, as well as to ensure that an asynchronous
DSYNC signal will exactly synchronize all the converters.
The second use of DSYNC is to reset the modulator count
to zero in order to obtain valid data as quickly as possible.
For example, if the analog input signal is changed signifi-
cantly on the ADS1250, the current conversion cycle will be
a mix of the old data and the new data. Five conversions are
needed for the digital filter to settle. Therefore, the sixth
conversion will be valid data. However, if the analog input
signal is changed and then DSYNC is used to reset the
modulator count, the modulator data at the end of the current
conversion cycle will be entirely from the new signal. After
four additional conversion cycles, the output data will be
completely valid. Note that the conversion cycle in which
DSYNC is used will be slightly longer than normal. Its
length will depend on when DSYNC was set.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ADS1250U | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC SpeedPlus 20-Bit Data Acq System RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1250U/1K | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC SpeedPlus 20-Bit Data Acq System RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1250U/1KG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC SpeedPlus 20-Bit Data Acq System RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1250UG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC SpeedPlus 20-Bit Data Acq System RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1251 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:24-Bit, 20kHz, Low-Power ANALOG-TO-DIGITAL CONVERTER |
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