參數(shù)資料
型號(hào)： ADS1250
英文描述： 20-Bit Data Acquisition System ANALOG-TO-DIGITAL CONVERTER
中文描述： 20位數(shù)據(jù)采集系統(tǒng)的模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù)： 13/20頁(yè)
文件大?。?/td> 196K
代理商： ADS1250
13
ADS1250
t
2
t
1
DRDY
MSB
written
to DOR
DOR
write
complete
CS
DOUT
FIGURE 14. DRDY Pulse (using CS).
FIGURE 15. DRDY Pulse (CS HIGH).
FIGURE 13. DRDY Pulse (CS tied LOW).
CS
The CS signal controls the state of DOUT. If CS is HIGH,
DOUT is in a high-impedance state. When CS is LOW,
DOUT drives the bus.
DRDY
The DRDY signal is used to indicate that new data has been
loaded into the data output register and is ready to be read.
The operation of DRDY depends on how the CS signal is
used. The specifics of the three communications methods
are described in the Serial Interface section.
In the first case, which is typical for three-wire serial
communications (CS tied LOW), DRDY would normally be
HIGH. The result of the A/D conversion would be written to
the DOR from MSB to LSB in the time defined by t
1
. The
DRDY line would then pulse LOW for time defined by t
2
,
as shown in Figure 13.
In the second case, which is typical for four-wire serial
communications (CS used), DRDY would normally be HIGH.
The result of the A/D conversion would be written to the DOR
from MSB to LSB in the time defined by t
1
. The DRDY would
go LOW after the DOR write is completed. After taking CS
LOW, the DRDY line would remain LOW for the time
defined by t
2
, as shown in Figure 14.
MSB to LSB in the time defined by t
3
. The DRDY line
would stay HIGH for the time defined by t
4
, as shown in
Figure 15.
Reading DRDY during the time shown by t
1
and t
3
(Figures
13, 14, and 15) will result in invalid data being read. This is
due to the fact that writes to the DOR are not blocked.
Subsequently, a read from DOR during this time will result
in a combination of old and new data.
SERIAL INTERFACE
The ADS1250 includes a simple serial interface which can
be connected to microcontrollers and digital signal proces-
sors in a variety of ways. Communications with the ADS1250
can commence on the first detection of the DRDY pulse
after power up, although data will not be valid until the sixth
conversion.
It is important to note that the data from the ADS1250 is a 20-
bit result transmitted MSB-first in Binary Two’s Complement
format, as shown in Table IV.
The entire 20-bit result can be read out of the device by simply
providing 20 SCLKs during serial communication with the
part. However, the most common method of communicating
with the device is with a standard SSI interface, such as SPI.
This protocol is based on 8-bit or 16-bit data transfers. It is
possible to use a standard 8-bit or 16-bit data transfer with the
ADS1250. For instance, if only 16 bits of data are read, the
internal bit pointer will automatically reset to the MSB of the
DOR on the next DRDY pulse. This will ensure that the next
read from the DOR will begin with the MSB of newly
converted data. If more than 20 bits of data are read, the data
will be 0 padded. Therefore, if 24 bits of data are read from the
ADS1250, the lowest four bits of the 24-bit data transfer are
read as 0s (0 padded).
The only limitation on SCLK is that it cannot be higher than
9.6MHz. Therefore, it is possible to run CLK at a lower
frequency than SCLK. For instance, it is possible to run
CLK at 23.040kHz for a 60Hz notch, and run SCLK at
9.6MHz to achieve high-speed serial communications. Ad-
ditionally, the data must be clocked out before the next
DRDY to ensure valid data, as described in the DRDY
section.
TABLE IV. ADS1250 Data Format (Binary Two's Comple-
ment).
DIFFERENTIAL VOLTAGE INPUT
DIGITAL OUTPUT (HEX)
+Full Scale
Zero
–Full Scale
7FFFFH
00000H
80000H
t
2
t
1
DRDY
DOUT
MSB
written
to DOR
DOR
write
complete
In the third case, CS is left HIGH, which may be used if data
is only periodically read from the ADS1250. In this case,
DRDY would normally be LOW. DRDY would go HIGH
immediately prior to the MSB being written to the DOR.
The result of the A/D conversion would be written from
t
3
t
4
MSB
written
to DOR
DRDY
DOR
write
complete
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ADS1250U 功能描述:模數(shù)轉(zhuǎn)換器 - ADC SpeedPlus 20-Bit Data Acq System RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS1250U/1K 功能描述:模數(shù)轉(zhuǎn)換器 - ADC SpeedPlus 20-Bit Data Acq System RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS1250U/1KG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC SpeedPlus 20-Bit Data Acq System RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS1250UG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC SpeedPlus 20-Bit Data Acq System RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS1251 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:24-Bit, 20kHz, Low-Power ANALOG-TO-DIGITAL CONVERTER
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