參數(shù)資料
型號(hào)： ADS1191IPBSR
廠商： Texas Instruments
文件頁(yè)數(shù)： 21/67頁(yè)
文件大小： 0K
描述： IC AFE 16BIT 8KSPS 1CH 32TQFP
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 16
通道數(shù)： 1
電壓 - 電源，模擬： 2.7 V ~ 5.25 V
電壓 - 電源，數(shù)字： 1.7 V ~ 3.6 V
封裝/外殼： 32-TQFP
供應(yīng)商設(shè)備封裝： 32-TQFP（5x5）
包裝： 帶卷 (TR)
START Opcode
START Pin
DIN
4 / f
CLK
DRDY
or
t
DR
t
SETTLE
SBAS566A – DECEMBER 2011 – REVISED SEPTEMBER 2012
START
The START pin must be set high or the START command sent to begin conversions. When START is low or if
the START command has not been sent, the device does not issue a DRDY signal (conversions are halted).
When using the START opcode to control conversion, hold the START pin low. The ADS1191/2 feature two
modes to control conversion: continuous mode and single-shot mode. The mode is selected by SINGLE_SHOT
(bit 7 of the CONFIG1 register). In multiple device configurations the START pin is used to synchronize devices
(see the Multiple Device Configuration subsection of the SPI Interface section for more details).
Settling Time
The settling time (tSETTLE) is the time it takes for the converter to output fully settled data when the START signal
is pulled high. Once START is pulled high, DRDY is also pulled high. The next falling edge of DRDY indicates
that data are ready. Figure 32 shows the timing diagram and Table 5 shows the settling time for different data
rates. The settling time depends on fCLK and the decimation ratio (controlled by the DR[2:0] bits in the CONFIG1
register). Table 4 shows the settling time as a function of tCLK. Note that when START is held high and there is a
step change in the input signal, it takes 3 tDR for the filter to settle to the new value. Settled data are available on
the fourth DRDY pulse. Settling time number uncertainty is one tMOD cycle. Therefore, it is recommended to add
one tMOD cycle delay before issuing SCLK to retrieve data.
(1) Settling time uncertainty is one tMOD cycle.
Figure 32. Settling Time
Table 5. Settling Time for Different Data Rates
DR[2:0]
SETTLING TIME(1)
UNIT(2)
000
4100
tMOD
001
2052
tMOD
010
1028
tMOD
011
516
tMOD
100
260
tMOD
101
132
tMOD
110
68
tMOD
111
—
(1)
Settling time uncertainty is one tMOD cycle.
(2)
tMOD = 4 tCLK for CLK_DIV = 0 and tMOD = 16 tCLK for CLK_DIV = 1.
28
Copyright 2011–2012, Texas Instruments Incorporated
Product Folder Links: ADS1191 ADS1192
相關(guān)PDF資料
PDF描述
V375C2M50BF CONVERTER MOD DC/DC 2V 50W
MAX9015AEKA+T IC COMPARATOR SGL SOT23-8
V375C2M50BL2 CONVERTER MOD DC/DC 2V 50W
V375C2M50BL CONVERTER MOD DC/DC 2V 50W
MCP3901A0T-E/ML IC AFE 24BIT 64KSPS 2CH 20QFN
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADS1191IRSMR 制造商:Texas Instruments 功能描述:AFE General Purpose 1ADC 24-Bit 1.8V/3V 32-Pin VQFN EP T/R 制造商:Texas Instruments 功能描述:IC AFE 16BIT 8KSPS 1CH 32VQFN 制造商:Texas Instruments 功能描述:Low Pwr Int AFE for ECG App
ADS1191IRSMT 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Cmplt Lw Pwr Intgrtd AFE for ECG apps RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS1192 制造商:TI 制造商全稱:Texas Instruments 功能描述:Low-Power, 2-Channel, 16-Bit Analog Front-End for Biopotential Measurements
ADS1192ECG-FE 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開(kāi)發(fā)工具 ADS1192 Demo Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V
ADS1192IPBS 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Low Pwr Integ AFE RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*