參數(shù)資料
型號: ADS1191IPBSR
廠商: Texas Instruments
文件頁數(shù): 13/67頁
文件大?。?/td> 0K
描述: IC AFE 16BIT 8KSPS 1CH 32TQFP
標準包裝: 1,000
位數(shù): 16
通道數(shù): 1
電壓 - 電源,模擬: 2.7 V ~ 5.25 V
電壓 - 電源,數(shù)字: 1.7 V ~ 3.6 V
封裝/外殼: 32-TQFP
供應商設備封裝: 32-TQFP(5x5)
包裝: 帶卷 (TR)
H(f) =
3
sin
N f
p
f
MOD
N
sin
pf
f
MOD
H(z) =
3
1
Z
-
- N
1
Z
-
- 1
160
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
0.001
0.01
0.1
1
Normalized Frequency (fIN/fMOD)
Power
Spectral
Density
(dB)
G001
SBAS566A – DECEMBER 2011 – REVISED SEPTEMBER 2012
ADC
ΔΣ Modulator
Each channel of the ADS1191/2 has a 16-bit
ΔΣ ADC. This converter uses a second-order modulator optimized
for low-power applications. The modulator samples the input signal at the rate of fMOD = fCLK/4 or fCLK/16, as
determined by the CLK_DIV bit. In both cases, the sampling clock has a typical value of 128 kHz. As in the case
of any
ΔΣ modulator, the noise of the ADS1191/2 is shaped until fMOD/2, as shown in Figure 20. The on-chip
digital decimation filters explained in the next section can be used to filter out the noise at higher frequencies.
These on-chip decimation filters also provide antialias filtering. This feature of the
ΔΣ converters drastically
reduces the complexity of the analog antialiasing filters that are typically needed with nyquist ADCs.
Figure 20. Power Spectral Density (PSD) of a
ΔΣ Modulator (4-Bit Quantizer)
DIGITAL DECIMATION FILTER
The digital filter receives the modulator output and decimates the data stream. By adjusting the amount of
filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, filter less for
higher data rates. Higher data rates are typically used in ECG applications for implement software pace detection
and ac lead-off detection.
The digital filter on each channel consists of a third-order sinc filter. The decimation ratio on the sinc filters can
be adjusted by the DR bits in the CONFIG1 register (see the Register Map section for details). This setting is a
global setting that affects all channels and, therefore, in a device all channels operate at the same data rate.
Sinc Filter Stage (sinx/x)
The sinc filter is a variable decimation rate, third-order, low-pass filter. Data are supplied to this section of the
filter from the modulator at the rate of fMOD. The sinc filter attenuates the high-frequency noise of the modulator,
then decimates the data stream into parallel data. The decimation rate affects the overall data rate of the
converter.
Equation 5 shows the scaled Z-domain transfer function of the sinc filter.
(5)
The frequency domain transfer function of the sinc filter is shown in Equation 6.
where:
N = decimation ratio
(6)
20
Copyright 2011–2012, Texas Instruments Incorporated
Product Folder Links: ADS1191 ADS1192
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