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參數(shù)資料
| 型號： | ADS1191IPBSR |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 10/67頁 |
| 文件大小： | 0K |
| 描述： | IC AFE 16BIT 8KSPS 1CH 32TQFP |
| 標準包裝： | 1,000 |
| 位數(shù)： | 16 |
| 通道數(shù)： | 1 |
| 電壓 - 電源，模擬： | 2.7 V ~ 5.25 V |
| 電壓 - 電源，數(shù)字： | 1.7 V ~ 3.6 V |
| 封裝/外殼： | 32-TQFP |
| 供應商設備封裝： | 32-TQFP（5x5） |
| 包裝： | 帶卷 (TR) |
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CMRR=20log
Gain
2
2e3
C
60
p
D
P
105
100
95
90
85
5
10
15
20
25
CFILTER (nF)
THD
(dB)
G025
PgaP
R
150kW
2
R
60k
(forGain=6)
W
1
R
150kW
2
FromMuxP
PgaN
FromMuxN
R =2kW
S
R =2kW
S
C
4.7nF
FILTER
PGA1P
PGA1N
C
P1
C
P2
SBAS566A – DECEMBER 2011 – REVISED SEPTEMBER 2012
PGA SETTINGS AND INPUT RANGE
The PGA is a differential input/differential output amplifier, as shown in Figure 18. It has seven gain settings (1,
2, 3, 4, 6, 8, and 12) that can be set by writing to the CHnSET register (see the CH1SET and CH2SET Registers
in the Register Map section for details). The ADS1191/2 have CMOS inputs and hence have negligible current
noise.
Figure 18. PGA Implementation
The resistor string of the PGA that implements the gain has 360 k
Ω of resistance for a gain of 6. This resistance
provides a current path across the outputs of the PGA in the presence of a differential input signal. This current
is in addition to the quiescent current specified for the device in the presence of a differential signal at the input.
The output of PGA is filtered by an RC filter before it goes to the ADC. The filter is formed by an internal resistor
RS = 2 kΩ and an external capacitor CFILTER (4.7 nF, typical). This filter acts as an anti-aliasing filter with the –3-
dB bandwidth of 8.4 kHz. The internal RS resistor is accurate to 15% so actual bandwidth will vary. This RC filter
also suppresses the glitch at the output of PGA caused by ADC sampling. The minimum value of CEXT that can
be used is 4 nF. A larger value CFILTER capacitor can be used for increased attenution at higher frequencies for
anti-aliasing purposes. The tradeoff is that a larger capacitor value gives degraded THD performance. See
Figure 19. THD versus CFILTER Value
Special care must be taken in PCB layout to minimize the parasitic capacitance CP1/CP2. The absolute value of
these capacitances must be less than 20 pF. Ideally, CFILTER should be placed right at the pins to minimize these
capacitors. Mismatch between these capacitors will lead to CMRR degradation. Assuming everything else is
perfectly matched, the 60 Hz CMRR as a function of this mismatch is given by Equation 2.
(2)
where
ΔCP = CP1 – CP2
18
Copyright 2011–2012, Texas Instruments Incorporated
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| ADS1192ECG-FE | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS1192 Demo Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
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