參數(shù)資料
型號(hào)： ADP5589ACBZ-02-R7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 8/52頁(yè)
文件大小： 0K
描述： IC PORT EXPANDER 19I/O 25WLSCP
產(chǎn)品變化通告： 8mm Carrier Tape Changes 28/Feb/2012
標(biāo)準(zhǔn)包裝： 3,000
系列： *
ADP5589
Data Sheet
Rev. B | Page 16 of 52
LOGIC BLOCKS
Several of the ADP5589 I/O lines can be used as inputs and
outputs for implementing some common logic functions.
The R1, R2, and R3 I/O pins can be used as inputs, and the R0
I/O pin can be used as an output for Logic Block 1.
The C8, C7, and C6 I/O pins can be used as inputs, and the C9
I/O pin can be used as an output, for Logic Block 2. It is also
possible to cascade the output of Logic Block 1 as an alternate
input for Logic Block 2 (LY1 is used instead of LA2).
The outputs from the logic blocks can be configured to generate
interrupts. They can also be configured to generate events on
the FIFO. The LCK_TRK_LOGIC (0x4D[4]) bit can be used
to allow logic events (programmed for FIFO updating) to be
tracked when the keypad is locked.
Figure 21 and Figure 22 show detailed diagrams of the internal
make-up of each logic block, illustrating the possible logic
functions that can be implemented.
GPI EVENT
I2C BUSY?
KEY EVENT
LOGIC EVENT
(R1) LA1
LC1
LB1
LA1_INV
LOGIC
EVENT/INT
GENERATOR
D
CLR
Q
SET
LB1_INV
LC1_INV
FF1_SET
FF1_CLR
R3_EXTEND_CFG[1:0]
LOGIC1_SEL[2:0]
LY1_INV
LA2_INV
LB2_INV
LC2_INV
FF2_SET
FF2_CLR
C6_EXTEND_CFG
LOGIC2_SEL[2:0]
LY2_INV
(R2)
(R3)
(C8) LA2
LC2
LB2
(C7)
(C6)
LOGIC BLOCK1
LOGIC BLOCK2
LY1 (R0)
LY2 (C9)
LOGIC1_INT
LOGIC2_INT
LOGIC1_INT_LEVEL
FIFO
UPDATE
LOGIC2_INT_LEVEL
LOGIC1_EVENT_EN
LOGIC2_EVENT_EN
OVRFLOW_INT
EVENT_INT
LCK_TRK_LOGIC
RESET_TRIGGER_TIME[2:0]
RESET1_EVENT_A[7:0]
RESET1_EVENT_B[7:0]
RESET1_EVENT_C[7:0]
RESET2_EVENT_A[7:0]
RESET2_EVENT_B[7:0]
FIFO
EC[4:0]
D
CLR
Q
SET
09714-
019
Figure 20. Logic Blocks Overview
LA1_INV
MUX
000
001
SEL[2:0]
OUT
010
011
100
101
110
111
SEL
OUT
0
1
GND
AND1
OR1
XOR1
FF1
IN_LA1
IN_LB1
IN_LC1
LA1
IN_LA1
SEL
OUT
0
1
AND1
IN_LA1
IN_LB1
IN_LC1
R3_EXTEND_CFG[1:0] = 01
LOGIC1_SEL[2:0]
LY1_INV
SEL
OUT
0
1
LY1
LB1_INV
SEL
OUT
0
1
LB1
IN_LB1
LC1_INV
SEL
OUT
0
1
LC1
IN_LC1
FF1_SET
FF1_CLR
SEL
OUT
0
1
OR1
IN_LA1
IN_LB1
IN_LC1
AND
OR
SEL
OUT
0
1
XOR1
IN_LA1
IN_LB1
IN_LC1
IN_LA1
IN_LB1
IN_LC1
XOR
D
CLR
Q
SET
0
1
SEL
OUT
09714-
020
FF1
Figure 21. Logic Block 1
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