參數(shù)資料
型號(hào)： ADN2855ACPZ-R7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 7/20頁(yè)
文件大?。?/td> 0K
描述： IC CLK/RECOVERY MULTI 32LFCSP
標(biāo)準(zhǔn)包裝： 1,500
類(lèi)型： 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR）
PLL： 是
主要目的： GPON，BPON，GEPON
輸入： CML
輸出： LVDS
電路數(shù)： 1
比率 - 輸入:輸出： 1:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 200MHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 帶卷 (TR)
ADN2855
Rev. A | Page 15 of 20
APPLICATIONS INFORMATION
PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used for optimal
performance.
Power Supply Connections and Ground Planes
Use of one low impedance ground plane is recommended. The
VEE pins should be soldered directly to the ground plane to
reduce series inductance. If the ground plane is an internal
plane and connections to the ground plane are made through
vias, multiple vias can be used in parallel to reduce the series
inductance. The exposed pad should be connected to the GND
plane using plugged vias so that solder does not leak through
the vias during reflow.
Use of a 10 F electrolytic capacitor between VCC and VEE is
recommended at the location where the 3.3 V supply enters the
PCB. When using 0.1 F and 1 nF ceramic chip capacitors, they
should be placed between the IC power supply VCC and VEE,
as close as possible to the ADN2855 VCC pins.
If connections to the supply and ground are made through vias,
the use of multiple vias in parallel helps to reduce series inductance.
Refer to the schematic in Figure 17 for recommended connections.
By using adjacent power supply and GND planes, excellent high
frequency decoupling can be realized by using close spacing
between the planes. This capacitance is given by
[ ]
A/d
C
r
PLANE
ε
88
.
0
pf =
where:
εr is the dielectric constant of the PCB material.
A is the area of the overlap of power and GND planes (cm2).
d is the separation between planes (mm).
For FR-4, εr = 4.4 mm and 0.25 mm spacing, CPLANE ≈ 15 pF/cm2.
06660-
015
VCO
FREQ,
LOCK
DET
PHASE
DET
PHASE
SHIFTER
LOOP
FILTER
LOOP
FILTER
I2C
DESERIALIZER
DIVIDER
DATA
RETIMING
REFCLKP,
REFCLKN
DATxP,
DATxN
CLKOUTP,
CLKOUTPN
CF1
CF2
VCC
0.1F
0.47F
VCC
VEE
PIN
NIN
PIN
VPD
NIN
LAOUTP
LAOUTN
SD
A
S
CK
S
ADDR[
2:
1]
D
A
TA
V
RESET
VEE
V
CC
R
ESET
S
Q
UE
L
CH
SQUELCH
CML INPUT
BUFFER
2
4 × 2
2
0.1F
1nF
VCC
OLT SYSTEM
CLOCK
ADN2855
OLT MAC
VCC
0.1F
Figure 17. Typical Application Circuit
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