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參數(shù)資料
| 型號： | ADN2855ACPZ-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK/RECOVERY MULTI 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 時鐘和數(shù)據(jù)恢復(fù)（CDR） |
| PLL： | 是 |
| 主要目的： | GPON，BPON，GEPON |
| 輸入： | CML |
| 輸出： | LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 200MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
ADN2855
Rev. A | Page 14 of 20
OUTPUT MODES
Parallel or Serial Output Mode
The output of the ADN2855 can be configured in a 4-bit
parallel output nibble mode, or it can be configured in a
serial output mode. The default mode of operation is for
the Rx data to be deserialized and output in a 4-bit nibble,
present at DATxP/DATxN, where the earliest bit is present
on DAT3P/DAT3N. Setting Bit CTRLC[5] = 1 reverses the
order of the DATxP/DATxN bus such that the earliest bit is
present on DAT0P/DAT0N.
Setting bit CTRLD[7] = 1 puts the device into serial output
mode. In this mode, the Rx data is present on DAT0P/DAT0N.
Double Data Rate Mode
The default output mode for the ADN2855 is for a 4-bit deseria-
lized output with a full rate output clock, where the output
data switches on the rising edge of the output clock. When
the ADN2855 is programmed to be in parallel output mode
(CTRLD[7] = 0), setting CTRLC[4] = 1 puts the ADN2855
clock output through divide-by-two circuitry, allowing direct
interfacing to FPGAs that support data clocking on both rising
and falling edges.
When the ADN2855 is in serial output mode (deserializer off),
CTRLD[7] = 1, the default is for a half rate output clock where
the data switches on both falling and rising edges of the output
clock. Setting CTRLD[0] = 1 sets the serial clock output into full
rate mode so that the output data switches only on the rising edges
of the output clock.
RxCLK Phase Adjust
The ADN2855 provides the option of adjusting the phase of the
output clock with respect to the parallel output data. In parallel
mode, the duration of each bit is 4 UI wide, due to the deserializa-
tion. There are three additional phase adjust options other than
the baseline (that is, CLK edge in the center of the data eye): +2 UI,
+0.5 UI, and 1.5 UI. The output clock phase adjustment feature
is accessed via CTRLC[3:2]. See Table 10 for details.
DISABLE OUTPUT BUFFERS
The ADN2855 provides the option of disabling the output buffers
for power savings. The clock output buffers can be disabled by
setting CTRLD[5] = 1. For additional power savings (for example,
in a low power standby mode), the data output buffers can also
be disabled by setting CTRLD[6] = 1.
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|---|---|
| ADN2855XCPZ | 功能描述:IC CLK DATA REC GPON 200MHZ 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):上次購買時間 PLL:是 主要用途:GPON，BPON，GEPON 輸入:CML 輸出:LVDS 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:是/是 頻率 - 最大值:200MHz 電壓 - 電源:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-WFQFN 裸露焊盤 供應(yīng)商器件封裝:32-LFCSP-VQ（5x5） 標(biāo)準(zhǔn)包裝:1 |
| ADN2860 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3-Channel Digital Potentiometer with Nonvolatile Memory |
| ADN2860ACPZ25 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| ADN2860ACPZ250 | 制造商:Analog Devices 功能描述: |
| ADN2860ACPZ250-RL7 | 功能描述:IC POT DGTL 3CH 250K 24-LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:XDCP™ 接片:256 電阻（歐姆）:100k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 ±300 ppm/°C 存儲器類型:非易失 接口:I²C（設(shè)備位址） 電源電壓:2.7 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) |
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