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| 型號： | ADN2855ACPZ-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK/RECOVERY MULTI 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR） |
| PLL： | 是 |
| 主要目的： | GPON，BPON，GEPON |
| 輸入： | CML |
| 輸出： | LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 200MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
Multirate 155 Mbps/622 Mbps/1244 Mbps/1250 Mbps
Burst Mode Clock and Data Recovery IC with Deserializer
ADN2855
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
2009–2013 Analog Devices, Inc. All rights reserved.
FEATURES
Serial data input
155.52 Mbps/622.08 Mbps/1244.16 Mbps/1250.00 Mbps
12-bit acquisition time
4-bit parallel LVDS output interface
Patented dual-loop clock recovery architecture
Integrated PRBS generator
Byte rate reference clock
Loss-of-lock indicator
Supports double data rate (DDR)-compatible FPGA
I2C interface to access optional features
Single-supply operation: 3.3 V
Power
670 mW typical in serial output mode
825 mW typical in deserializer mode
5 mm × 5 mm, 32-lead LFCSP
APPLICATIONS
Passive optical networks
GPON/BPON/GEPON OLT receivers
GENERAL DESCRIPTION
The ADN2855 is a burst mode clock and data recovery IC
designed for GPON/BPON/GEPON optical line terminal (OLT)
receiver applications. The part can operate at 155.52 Mbps,
622.08 Mbps, 1244.16 Mbps, or 1250.00 Mbps data rates, selectable
via the I2C interface.
The ADN2855 frequency locks to the OLT reference clock and
aligns to the input data within 12 bits of the start of the preamble.
The device provides a full rate or an optional half rate output
clock for a double data rate (DDR) interface to an FPGA or
digital ASIC.
All specifications are quoted for 40°C to +85°C ambient tempera-
ture, unless otherwise noted. The ADN2855 is available in a
compact 5 mm × 5 mm, 32-lead chip scale package.
FUNCTIONAL BLOCK DIAGRAM
2
RESET
DATAV
DATxP,
DATxN
2
VCC
VEE
SDA
SCK
CF1
CF2
PIN
NIN
CML INPUT
BUFFER
VCO
PHASE
SHIFTER
PHASE
DETECT
FREQUENCY/
LOCK
DETECT
DATA
RE-TIMING
DIVIDER
I2C
DESERIALIZER
LOOP
FILTER
LOOP
FILTER
4 × 2
REFCLKP,
REFCLKN
06660-
001
CLKOUTP,
CLKOUTN
SQUELCH
ADN2855
Figure 1.
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