參數(shù)資料
型號: ADE7754ARRL
廠商: ANALOG DEVICES INC
元件分類: 模擬信號調(diào)理
英文描述: ADE7754
中文描述: SPECIALTY ANALOG CIRCUIT, PDSO24
封裝: MS-013AD, SOIC-24
文件頁數(shù): 28/44頁
文件大?。?/td> 630K
代理商: ADE7754ARRL
REV. PrG 01/03
PRELIMINARY TECHNICAL DATA
ADE7754
28
The total apparent power calculated by the ADE7754 de-
pends on the configuration of the VAMOD bits in the
VAMode register. Each term of the formula can be disabled
or enabled by the setting VASEL bits respectively to logic 0
or logic 1 in the VAMode register. The different configura-
tions are described in Table IV.
VA-
VASEL0
VASEL1
MOD
0d V
Arms
x I
Arms
+ V
Brms
x I
Brms
1d V
Arms
xI
Arms
+(V
Arms+
V
Crms
)/2xI
Brms
+ V
Crms
x I
Crms
2d V
Arms
x I
Arms
+ V
Arms
x I
Brms
VASEL2
+ V
Crms
x I
Crms
+ V
Crms
x I
Crms
Table IV - Total Apparent Power calculation
Note: V
Arms
, V
Brms
, V
Crms
, I
Arms
, I
Brms
and I
Crms
represent
respectively the voltage and current channels RMS values of
the corresponding registers.
For example, for VAMOD = 1, the exact formula that is used
to process the Apparent Power is:
Total Apparent Power
V
I
AVAG
2
12
)
I
V
V
Arms
Arms
Arms
Crms
=
+
+
+
2
1
(
+
+
+
1
2
1
2
12
12
BVAG
V
I
CVAG
Brms
Crms
Crms
Depending on the polyphase meter configuration, the appro-
priate formula should be chosen to calculate the Apparent
Energy. The American ANSI C12.10 standard defines the
different configurations of the meter. Table V describes
which mode should be chosen in these different configura-
tions.
ANSI Meter Form
VAMOD
5S/13S
3-wire Delta
0
6S/14S
4-wire Wye
1
8S/15S
4-wire Delta
2
9S/16S
4-wire Wye
0
VASEL
3 or 5 or 6
7
7
7
Table V - Meter form configuration
Different gain calibration parameters are offered in the
ADE7754 to cover the calibration of the meter in different
configurations. These registers, APGAIN, VGAIN and
VAGAIN, have different purposes in the signal processing of
the ADE7754.
APGAIN registers affect the Apparent power calculation but
should be used only for Active Power calibration. VAGAIN
registers are used to calibrate the Apparent Power calcula-
tion.
VGAIN registers have the same effect as VAGAIN registers
when VAMOD=0 or 2. They should be left at their default
value in these modes. VGAIN registers should be used to
compensate gain mismatches between channels in
VAMOD=1.
As mentioned before, the offset compensation of the Phase
Apparent Power calculation is done in each individual RMS
measurement signal processing -see
Apparent Power Offset com-
pensation.
APPARENT ENERGY CALCULATION
The Apparent Energy is given as the integral of the Apparent
Power.
=
The ADE7754 achieves the integration of the Apparent
Power signal by continuously accumulating the Apparent
Power signal in an internal non-readable 49-bit register. The
Apparent Energy register (VAENERGY[23:0]) represents
the upper 24 bits of this internal register. This discrete time
accumulation or summation is equivalent to integration in
continuous time. Equation 22 below expresses the relation-
ship
Apparent Energy
Apparent Power t dt
( )
(21)
Apparent Energy
Lim
Apparent Power nT
T
=
×
=
0
0
(
)
(22)
Where n is the discrete time sample number and T is the
sample period.
The discrete time sample period (T) for the accumulation
register in the ADE7754 is 1.2μs (12/10MHz).
Figure 35 shows a graphical representation of this discrete
time integration or accumulation. The Apparent Power
signal is continuously added to the internal register. This
addition is a signed addition even if the Apparent Energy
remains theoretically always positive.
48
0
+
+
Σ
TOTAL APPARENT POWER
00000h
D1B71h
time (nT)
T
TOTAL APPARENT POWER ARE
ACCUMULATED (INTEGRATED) IN
THE APPARENT ENERGY REGISTER
Apparent Power
Signal - P
T
48
0
VAENERGY[23:0]
VADIV
23
0
Figure 35-ADE7754 Apparent Energy calculation
The upper 49-bit of the internal register are divided by
VADIV. If the value in the VADIV register is equal to 0 then
the internal active Energy register is divided by 1. VADIV is
an 8-bit unsigned register. The upper 24-bit are then written
in the 24-bit Apparent Energy register (VAENERGY[23:0]).
RVAENERGY register (24 bits long) is provided to read the
Apparent Energy. This register is reset to zero after a read
operation.
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