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參數(shù)資料
| 型號： | ADE7754ARRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | ADE7754 |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO24 |
| 封裝： | MS-013AD, SOIC-24 |
| 文件頁數(shù)： | 12/44頁 |
| 文件大?。?/td> | 630K |
| 代理商： | ADE7754ARRL |
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REV. PrG 01/03
PRELIMINARY TECHNICAL DATA
ADE7754
–
12
–
CURRENT CHANNEL ADC
Figure 8 shows the ADC and signal processing chain for the
input IA of the current channels (same for IB and IC). In
waveform sampling mode the ADC outputs are signed 2’s
Complement 24-bit data word at a maximum of 26.0kSPS
(kilo Samples Per Second). The output of the ADC can be
scaled by ±50% by using the APGAINs register. While the
ADC outputs are 24-bit 2's complement value the maximum
full-scale positive value from the ADC is limited to 400000h
(+4,194,304d). The maximum full-scale negative value is
limited to C00000h (-4,194,304d). If the analog inputs are
over-ranged, the ADC output code clamps at these values.
With the specified full scale analog input signal of ±0.5V, the
ADC produces an output code between D70A3Eh (-
2,684,354) and 28F5C2h (+2,684,354). This is illustrated
in Figure 8. The diagram in Figure 8 shows a full-scale
voltage signal being applied to the differential inputs IAP and
IAN.
Current channel ADC Gain Adjust
The ADC gain in each phase of the Current Channel can be
adjusted by using the multiplier and Active Power Gain
register (AAPGAIN[11:0], BAPGAIN and CAPGAIN).
The gain of the ADC is adjusted by writing a 2’s complement
12-bit word to the Active Power Gain register. Below is the
expression that shows how the gain adjustment is related to
the contents of the Active Power Gain register.
Code
ADC
AAPGAIN
2
12
=
×
+
1
For example when 7FFh is written to the Active Power Gain
register the ADC output is scaled up by 50%. 7FFh = 2047d,
2047/2
12
= 0.5. Similarly, 800h = -2047 Dec (signed 2’s
Complement) and ADC output is scaled by –50%. These two
examples are illustrated graphically in Figure 8.
Current channel Sampling
The waveform samples of the current channel inputs may
also be routed to the WAVEFORM register (WAVMODE
register to select the speed and the phase) to be read by the
system master (MCU). The Active Energy and Apparent
Energy calculation will remain uninterrupted during wave-
form sampling.
When in waveform sample mode, one of four output sample
rates may be chosen by using bits 3 and 4 of the WAVMode
register (DTRT[1:0] mnemonic). The output sample rate
may be 26.0kSPS, 13.0kSPS, 6.5kSPS or 3.3kSPS—see
WAVMode register
. By setting the WSMP bit in the Interrupt
Mask register to logic one, the interrupt request output
IRQ
will go active low when a sample is available. The timing is
shown in Figure 9. The 24-bit waveform samples are trans-
ferred from the ADE7754 one byte (8-bits) at a time, with the
most significant byte shifted out first.
0 0
09 Hex
IRQ
DIN
DOUT
SCLK
Read from WAVEFORM
Current channel DATA - 24 bits
SGN
Figure 9 – Waveform sampling current channel
The interrupt request output IRQ stays low until the interrupt
routine reads the Reset Status register -
see ADE7754 Inter-
rupt.
Note:
If the WSMP bit in the interrupt MASK register is not
set to logic one, no data is available in the Waveform register.
HPF
IAP
IAN
ADC
PGA1
1
24
12
800Hex - 7FFHex
REFERENCE
AAPGAIN[11:0]
Vin
Vin
0V
000000h
400000h
C00000h
28F5C2h
D70A3Eh
+ 100% FS
- 100% FS
00000h
EB851Fh
28F5C2h
147AE1h
+ 100% FS
+ 50% FS
AAPGAIN[11:0]
- 100% FS
- 150% FS
D70A3Eh
C28F5Dh
+ 150% FS
- 50% FS
3D70A3h
000h
7FFh
800h
Analog
Input
Range
ADC Output
word Range
Channel 1
ACTIVE AND REACTIVE
POWER CALCULATION
WAVEFORM SAMPLE
REGISTER
1
Sinc
3
MULTIPLIER
Digital LPF
x1, GAIN[1:0]
0.5 V / GAIN1
CURRENT RMS
CALCULATION
100% FS
Figure 8 - ADC and signal processing in current channel
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