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參數(shù)資料
| 型號： | ADC1215S105HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Single 12-bit ADC 105 Msps with Input Buffer CMOS or LVDS DDR digital outputs |
| 封裝： | ADC1215S105HN/C1<SOT618-6 (HVQFN40)|<<http://www.nxp.com/packages/SOT618-6.html<1<Always Pb-free,;ADC1215S105HN/C1<SOT618-6 (HVQFN40)|<<http://www.nxp.com/packages/SOT618 |
| 文件頁數(shù)： | 34/42頁 |
| 文件大小： | 292K |
| 代理商： | ADC1215S105HN |
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ADC1215S_SER
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 13 January 2011
34 of 42
NXP Semiconductors
ADC1215S series
Single 12-bit ADC; input buffer; CMOS or LVDS DDR digital output
1 to 0
DATA_FORMAT[1:0]
R/W
output data format
offset binary
two’s complement
gray code
offset binary
00
01
10
11
Table 23.
Default values are highlighted.
Bit
Symbol
Output data standard control register (address 0011h) bit description
…continued
Access
Value
Description
Table 24.
Default values are highlighted.
Bit
Symbol
7 to 4
-
3
DAVINV
Output clock register (address 0012h) bit description
Access
Value
0000
Description
not used
output clock data valid (DAV) polarity
normal
inverted
DAV phase select
output clock shifted (ahead) by 3 ns
output clock shifted (ahead) by 2.5 ns
output clock shifted (ahead) by 2 ns
output clock shifted (ahead) by 1.5 ns
output clock shifted (ahead) by 1 ns
output clock shifted (ahead) by 0.5 ns
default value as defined in timing section
output clock shifted (delayed) by 0.5 ns
R/W
0
1
2 to 0
DAVPHASE[2:0]
R/W
000
001
010
011
100
101
110
111
Table 25.
Default values are highlighted.
Bit
Symbol
7 to 6
-
5 to 0
DIG_OFFSET[5:0]
Offset register (address 0013h) bit description
Access
Value
00
Description
not used
digital offset adjustment
+31 LSB
...
0
...
32 LSB
R/W
011111
...
000000
...
100000
Table 26.
Default values are highlighted.
Bit
Symbol
7 to 3
-
Test pattern register 1 (address 0014h) bit description
Access
Value
00000
Description
not used
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADC1215S105HN/C1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs |
| ADC1215S105HN/C1,5 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC SGL 12BT ADC 105MSPS IN BUF CMOS/LVDS DDR RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC1215S105HN-C1 | 制造商:Integrated Device Technology Inc 功能描述:HVQFN40 - Bulk |
| ADC1215S105HN-C18 | 制造商:Integrated Device Technology Inc 功能描述:HVQFN40 - Tape and Reel |
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