參數(shù)資料
型號(hào)： AD9992
廠商： Analog Devices, Inc.
英文描述： 12-Bit CCD Signal Processor with Precision Timing Generator
中文描述： 12位CCD信號(hào)處理器與精密時(shí)序發(fā)生器
文件頁(yè)數(shù)： 79/92頁(yè)
文件大?。?/td> 718K
代理商： AD9992
AD9992
Rev. 0 | Page 79 of 92
Address
33
34
Data
Bits
[5:0]
[13:8]
[16]
[0]
[1]
Default
Value
0
10
1
0
0
Update
Type
SCK
SCK
Name
RGPOSLOC
RGNEGLOC
RGH2POL
H1HBLKRETIME
H2HBLKRETIME
Description
RG rising edge location.
RG falling edge location.
RG polarity control. 0: inverse of Figure 18, 1: no inversion.
Retime H1, H2, HL HBLK to the internal clock. 0: no retime; 1: retime.
Recommended setting is retime enabled (1). Setting to 1 adds one cycle delay
to programmed HBLK positions.
Enable HBLK for HL output. 0: disable; 1: enable.
Enables wide H-clocks during HBLK interval. Set to 0 to disable.
H1 drive strength. 0: off; 1: 4.3 mA; 2: 8.6 mA; 3: 12.9 mA; 4: 4.3 mA;
5: 8.6 mA; 6: 12.9 mA; 7: 17.2 mA.
H2 drive strength (same range as H1DRV).
H3 drive strength (same range as H1DRV).
H4 drive strength (same range as H1DRV).
HL drive strength (same range as H1DRV).
RG drive strength (same range as H1DRV).
H5 drive strength (same range as H1DRV).
H6 drive strength (same range as H1DRV).
H7 drive strength (same range as H1DRV).
H8 drive strength (same range as H1DRV).
SHD sampling edge location.
SHP sampling edge location.
SHP width (controls input dc restore switch active time).
DOUT phase control, positive edge. Specifies location of DOUT.
DOUT phase control, negative edge. Always set to DOUTPHASEP plus
32 edges to maintain 50% duty cycle of internal DOUTPHASE clocking.
DCLK mode. 0: DCLK tracks DOUT; 1: DCLK phase is fixed.
Data output delay (t
OD
) with respect to DCLK rising edge.
0: no delay; 1: ~3 ns; 2: ~6 ns; 3: ~9 ns
Invert DCLK output. 0: no inversion, 1: inversion of DCLK.
Enable H-masking during CP operation.
35
[2]
[3]
[7:4]
[2:0]
0
0
4
1
SCK
HLHBLKRETIME
HL_HBLK_EN
HCLK_WIDTH
H1DRV
36
37
38
[6:4]
[10:8]
[14:12]
[18:16]
[22:20]
[2:0]
[6:4]
[10:8]
[14:12]
[5:0]
[11:6]
[17:12]
[5:0]
[11:6]
1
1
1
1
1
1
1
1
1
0
20
10
0
20
SCK
SCK
SCK
H2DRV
H3DRV
H4DRV
HLDRV
RGDRV
H5DRV
H6DRV
H7DRV
H8DRV
SHDLOC
SHPLOC
SHPWIDTH
DOUTPHASEP
DOUTPHASEN
[12]
[14:13]
0
0
DCLKMODE
DOUTDELAY
39
[15]
[2:0]
0
7
SCK
DCLKINV
CPHMASK
Table 34. Test Registers—Do Not Access
Address
Data Bits
3E ~ 4F
Default Value
Update
Name
Description
Test registers only. Do not access.
Table 35. Test Registers—Do Not Access
Address
Data Bits
50 ~ 6F
Default Value
Update Type
Name
Description
Test registers only. Do not access.
Table 36. Shutter and GPO Registers
Data
Bits
70
[2:0]
[5:3]
Address
Default
Value
0
0
Update
Type
VD
Name
PRIMARY_ACTION
SECOND_ACTION
Description
Selects action for primary and secondary counters.
0: idle (do nothing) autoreset on VD.
1: activate counter (primary: auto exposure/readout).
2: RapidShot: wrap/repeat counter.
3: ShotTimer: delay start of count.
4: ShotTimer with RapidShot.
5: SLR exposure (manual).
相關(guān)PDF資料
PDF描述
AD9992BBCZ 12-Bit CCD Signal Processor with Precision Timing Generator
AD9992BBCZRL 12-Bit CCD Signal Processor with Precision Timing Generator
AD9995KCP 12-Bit CCD Signal Processor with Precision Timing ⑩ Generator
AD9995KCPRL 12-Bit CCD Signal Processor with Precision Timing ⑩ Generator
AD9995 12-Bit CCD Signal Processor with Precision Timing ⑩ Generator
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9992_07 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit CCD Signal Processor with Precision Timing Generator
AD9992BBCZ 功能描述:IC CCD SGNL PROC 12BIT 105CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測(cè)器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件
AD9992BBCZRL 功能描述:IC CCD SGNL PROC 12BIT 105CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測(cè)器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件
AD9993BBCZ 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應(yīng)商器件封裝:196-CSPBGA（12x12） 標(biāo)準(zhǔn)包裝:1
AD9993BBCZRL 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應(yīng)商器件封裝:196-CSPBGA（12x12） 標(biāo)準(zhǔn)包裝:1,500
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