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參數(shù)資料
| 型號： | AD9992 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit CCD Signal Processor with Precision Timing Generator |
| 中文描述： | 12位CCD信號處理器與精密時序發(fā)生器 |
| 文件頁數(shù)： | 45/92頁 |
| 文件大?。?/td> | 718K |
| 代理商： | AD9992 |
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AD9992
VERTICAL TIMING EXAMPLE
To better understand how the AD9992 vertical timing
generation is used, consider the example CCD timing chart in
Figure 54. This example illustrates a CCD using a general
3-field readout technique. As described in the previous field
section, each readout field must be divided into separate regions
to perform each step of the readout. The sequence change
positions (SCP) determine the line boundaries for each region,
and the SEQx registers assign a particular V-sequence to each
region. The V-sequences contain the specific timing
information required in each region: V1 to V6 pulses (using V-
pattern groups), HBLK/CLPOB timing, and VSG patterns for
the SG active lines.
Rev. 0 | Page 45 of 92
This timing example requires four regions for each of the three
fields, labeled Region 0, Region 1, Region 2, and Region 3.
Because the AD9992 allows many individual fields to be pro-
grammed, FIELD0, FIELD1, and FIELD2 can be used to meet
the requirements of this timing example. The four regions for
each field are very similar in this example, but the individual
registers for each field allow flexibility to accommodate other
timing charts.
Region 0 is a high speed, vertical shift region. Sweep mode can
be used to generate this timing operation with the desired
number of high speed vertical pulses needed to clear any charge
from the CCD’s vertical registers.
Region 1 consists of only two lines and uses standard single-
line, vertical shift timing. The timing of this region area is the
same as the timing in Region 3.
Region 2 is the sensor gate line where the VSG pulses transfer
the image into the vertical CCD registers. This region might
require the use of the second V-pattern group for the SG
active line.
Region 3 also uses the standard single-line, vertical shift timing,
the same timing as Region 1. Four regions are required in each
of the three fields.
The timing for Region 1 and Region 3 is essentially the same,
reducing the complexity of the register programming. Other
registers need to be used during the actual readout operation.
These include the MODE registers, shutter control registers
(PRIMARY_ACTION, SUBCK, GPO for MSHUT, and VSUB
control) and AFE gain register.
Important Note Regarding Signal Polarities
When programming the AD9992 to generate the V1 to V24 and
SUBCK signals, the external V-driver circuit usually inverts
these signals. Carefully check the required timing signals needed
at the input and the output of the V-driver circuit being used and
adjust the polarities of the AD9992 outputs accordingly.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9992BBCZ | 12-Bit CCD Signal Processor with Precision Timing Generator |
| AD9992BBCZRL | 12-Bit CCD Signal Processor with Precision Timing Generator |
| AD9995KCP | 12-Bit CCD Signal Processor with Precision Timing ⑩ Generator |
| AD9995KCPRL | 12-Bit CCD Signal Processor with Precision Timing ⑩ Generator |
| AD9995 | 12-Bit CCD Signal Processor with Precision Timing ⑩ Generator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9992_07 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit CCD Signal Processor with Precision Timing Generator |
| AD9992BBCZ | 功能描述:IC CCD SGNL PROC 12BIT 105CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
| AD9992BBCZRL | 功能描述:IC CCD SGNL PROC 12BIT 105CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
| AD9993BBCZ | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應(yīng)商器件封裝:196-CSPBGA（12x12） 標(biāo)準(zhǔn)包裝:1 |
| AD9993BBCZRL | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應(yīng)商器件封裝:196-CSPBGA（12x12） 標(biāo)準(zhǔn)包裝:1,500 |
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