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參數(shù)資料
| 型號： | AD9992 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit CCD Signal Processor with Precision Timing Generator |
| 中文描述： | 12位CCD信號處理器與精密時序發(fā)生器 |
| 文件頁數(shù)： | 22/92頁 |
| 文件大?。?/td> | 718K |
| 代理商： | AD9992 |
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AD9992
Register
HBLKALT_PAT1
Rev. 0 | Page 22 of 92
Length Range
3b
Description
HBLK Mode 2, Odd Field Repeat Area 0 pattern, selected from even field
repeat areas previously defined.
HBLK Mode 2, Odd Field Repeat Area 1 pattern.
HBLK Mode 2, Odd Field Repeat Area 2 pattern.
HBLK Mode 2, Odd Field Repeat Area 3 pattern.
HBLK Mode 2, Odd Field Repeat Area 4 pattern.
HBLK Mode 2, Odd Field Repeat Area 5 pattern.
0 to 5 even repeat area
HBLKALT_PAT2
HBLKALT_PAT3
HBLKALT_PAT4
HBLKALT_PAT5
HBLKALT_PAT6
3b
3b
3b
3b
3b
0 to 5 even repeat area
0 to 5 even repeat area
0 to 5 even repeat area
0 to 5 even repeat area
0 to 5 even repeat area
HBLK
H-BLANK REPEATING PATTERN IS CREATED USING HBLKLEN AND HBLKREP REGISTERS
Figure 26. HBLK Repeating Pattern Using HBLKMODE = 1
H1/H3
H2/H4
HBLKSTART
HBLKTOGE1
HBLKTOGE2
HBLKEND
HBLKTOGE3
HBLKTOGE4
HBLKLEN
HBLKREP = 3
HBLKREP NUMBER 1
HBLKREP NUMBER 2
HBLKREP NUMBER 3
0
HBLK Mode 1 Operation
Multiple repeats of the HBLK signal are enabled by setting
HBLKMODE to 1. In this mode, the HBLK pattern can be
generated using a different set of registers: HBLKSTART,
HBLKEND, HBLKLEN, and HBLKREP, along with the six
toggle positions (see Figure 26).
Separate toggle positions are available for even and odd lines. If
alternation is not needed, the same values should be loaded into
the registers for even (HBLKTOGE) and odd (HBLKTOGO) lines.
Generating HBLK Line Alternation
HBLK Mode 0 and HBLK Mode 1 provide the ability to
alternate different HBLK toggle positions on even and odd
lines. HBLK line alternation can be used in conjunction with
V-pattern odd/even alternation or on its own. Separate toggle
positions are available for even and odd lines. If even/odd line
alternation is not required, the same values should be loaded into
the registers for even (HBLKTOGE) and odd (HBLKTOGO) lines.
Increasing H-Clock Width During HBLK
HBLK Mode 0 and HBLK Mode 1 allow the H1 to H8 pulse
width to be increased during the HBLK interval. As shown in
Figure 27, the H-clock frequency can be reduced by a factor of
1/2, 1/4, 1/6, 1/8, 1/10, 1/12, and so on, up to 1/30. To enable
this feature, the HCLK_WIDTH register (Address 0x34,
Bits [7:4]) is set to a value between 1 and 15. When this register
is set to 0, the wide HCLK feature is disabled. The reduced
frequency occurs only for H1 to H8 pulses that are located
within the HBLK area.
The HCLK_WIDTH register is generally used in conjunction
with special HBLK patterns to generate vertical and horizontal
mixing in the CCD.
Note that the wide HCLK feature is available only in HBLK
Mode 0 and HBLK Mode 1. HBLK Mode 2 does not support
wide HCLKs.
Table 11. HCLK Width Register
Register
Length
Description
HCLK_WIDTH
4b
Controls H1 to H8 width during
HBLK as a fraction of pixel rate
0: same frequency as pixel rate
1: 1/2 pixel frequency, that is,
doubles the HCLK pulse width
2: 1/4 pixel frequency
3: 1/6 pixel frequency
4: 1/8 pixel frequency
5: 1/10 pixel frequency
…
15: 1/30 pixel frequency
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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