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| 型號(hào)： | AD9992 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit CCD Signal Processor with Precision Timing Generator |
| 中文描述： | 12位CCD信號(hào)處理器與精密時(shí)序發(fā)生器 |
| 文件頁數(shù)： | 28/92頁 |
| 文件大小： | 718K |
| 代理商： | AD9992 |
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AD9992
Vertical Pattern Groups (VPAT)
The vertical pattern groups define the individual pulse patterns
for each V1 to V24 output signal. Table 12 summarizes the
registers available for generating each of the V-pattern groups.
The first, second, third, and fourth toggle positions (VTOG1,
VTOG2, VTOG3, and VTOG4) are the pixel locations within
the line where the pulse transitions. All toggle positions are
13-bit values, allowing their placement anywhere in the
horizontal line.
Rev. 0 | Page 28 of 92
More registers are included in the vertical sequence registers to
specify the output pulses. VPOL specifies the start polarity for
each signal; VSTART specifies the start position of the
V-pattern group within the line; VLEN designates the total
length of the V-pattern group, which determines the number of
pixels between each of the pattern repetitions when repetitions
are used.
The VSTART position is actually an offset value for each toggle
position. The actual pixel location for each toggle, measured
from the HD falling edge (Pixel 0), is equal to the VSTART
value plus the toggle position.
When the selected V-output is designated as a VSG pulse, either
the VTOG1/VTOG2 or VTOG3/VTOG4 pair is selected using
V-Sequence Address 0x02, VSGPATSEL. All four toggle positions
are not simultaneously available for VSG pulses.
All unused V-channels must have their toggle positions
programmed to either 0 or maximum value. This prevents
unpredictable behavior because the default values of the
V-pattern group registers are unknown.
Table 12. Vertical Pattern Group Registers
Register
Length
VTOG1
13b
VTOG2
13b
VTOG3
13b
VTOG4
13b
Description
First toggle position within line for each V1 to V24 output, relative to VSTART value
Second toggle position, relative to VSTART value
Third toggle position, relative to VSTART value
Fourth toggle position, relative to VSTART value
HD
V1
4
1
2
3
V2
1
2
3
V24
1
2
3
START POSITION OF VERTICAL PATTERN GROUP IS PROGRAMMABLE IN VERTICAL SEQUENCE REGISTERS.
PROGRAMMABLE SETTINGS:
1
START POLARITY (LOCATED IN V-SEQUENCE REGISTERS).
2
FIRST TOGGLE POSITION.
3
SECOND TOGGLE POSITION (THIRD AND FOURTH TOGGLE POSITIONS ALSO AVAILABLE FOR MORE COMPLEX PATTERNS).
4
TOTAL PATTERN LENGTH FOR ALL VERTICAL OUTPUTS (LOCATED IN VERTICAL SEQUENCE REGISTERS).
0
Figure 33. Vertical Pattern Group Programmability
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9992_07 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit CCD Signal Processor with Precision Timing Generator |
| AD9992BBCZ | 功能描述:IC CCD SGNL PROC 12BIT 105CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
| AD9992BBCZRL | 功能描述:IC CCD SGNL PROC 12BIT 105CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
| AD9993BBCZ | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應(yīng)商器件封裝:196-CSPBGA（12x12） 標(biāo)準(zhǔn)包裝:1 |
| AD9993BBCZRL | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應(yīng)商器件封裝:196-CSPBGA（12x12） 標(biāo)準(zhǔn)包裝:1,500 |
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