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參數(shù)資料
| 型號(hào)： | AD9985A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| 中文描述： | 110 MSPS/140 MSPS的模擬接口的平板顯示器 |
| 文件頁(yè)數(shù)： | 22/32頁(yè) |
| 文件大?。?/td> | 344K |
| 代理商： | AD9985A |
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AD9985A
Table 16. Active Hsync Override Settings
Override
Result
0
Autodetermines the active interface (power-up
default)
1
Override, Bit 3 determines the active interface
Rev. 0 | Page 22 of 32
0E
3
This bit is used under two conditions. It is used to
select the active Hsync when the override bit is set
(Bit 4). Alternately, it is used to determine the active
Hsync when not overriding, but both Hsyncs are
detected.
Table 17. Active Hsync Select Settings
Select
Result
0
Hsync input (power-up default)
1
Sync-on-green input
Active Hsync Select
0E
2
This bit inverts the polarity of the Vsync output
Table 18 shows the effect of this option.
Table 18. Vsync Output Invert Settings
Invert
Vsync Output
0
Invert (power-up default)
1
No invert
Vsync Output Invert
0E
1
This bit is used to override the automatic Vsync
selection. To override, set this bit to Logic 1. When
overriding, the active interface is set via Bit 0 in this
register.
Table 19. Active Vsync Override Settings
Override
Result
0
Autodetermines the active Vsync (power-up default)
1
Override, Bit 0 determines the active Vsync
Active Vsync Override
0E
0
This bit is used to select the active Vsync when the
override bit is set (Bit 1).
Table 20. Active Vsync Select Settings
Select
Result
0
Vsync input (power-up default)
1
Sync separator output
Active Vsync Select
0F
7
This bit determines the source of clamp timing.
Clamp Input Signal Source
Table 21. Clamp Input Signal Source Settings
Clamp Function
Result
0
Internally generated clamp signal (power-
up default)
1
Externally provided clamp signal
A 0 enables the clamp timing circuitry controlled by
clamp placement and clamp duration. The clamp
position and duration is counted from the leading
edge of Hsync.
A 1 enables the external CLAMP input pin. The three
channels are clamped when the clamp signal is active.
The polarity of clamp is determined by the clamp
polarity bit (Register 0x0F, Bit 6).
0F
6
This bit determines the polarity of the externally
provided clamp signal.
Table 22. Clamp Input Signal Polarity Settings
Clamp Function
Result
1
Active low (power-up default)
0
Active high
Clamp Input Signal Polarity
Logic 1 means that the circuit clamps when CLAMP is
low, and it passes the signal to the ADC when CLAMP
is high.
Logic 0 means that the circuit clamps when CLAMP is
high, and it passes the signal to the ADC when
CLAMP is low.
0F
5
This bit is used to select the active Coast source. The
choices are the COAST input pin or Vsync. If Vsync is
selected, the additional decision to use the Vsync
input pin or the output from the sync separator needs
to be made (Register 0x0E, Bits 1, 0).
Table 23. Power-Down Settings
Power-Down
Result
0
COAST input pin
1
Vsync (See the Coast Select section)
Coast Select
0F
4
This register is used to override the internal circuitry
that determines the polarity of the Coast signal going
into the PLL.
Coast Input Polarity Override
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| AD9985ABSTZ-110 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9985A/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9985A/PCBZ | 功能描述:KIT EVALUATION FOR AD9985A RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:Advantiv® 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| AD9985AABSTZ-110 | 制造商:Analog Devices 功能描述:ANALOG INTERFACE FOR FLAT PANEL DISPLAYS - Bulk |
| AD9985AAKSTZ-110 | 制造商:Analog Devices 功能描述:ANALOG INTERFACE FOR FLAT PANEL DISPLAYS - Bulk |
| AD9985AAKSTZ-140 | 制造商:Analog Devices 功能描述:ANALOG INTERFACE FOR FLAT PANEL DISPLAYS - Bulk |
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