- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373972 > AD9985A (Analog Devices, Inc.) 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays PDF資料下載
參數(shù)資料
| 型號： | AD9985A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| 中文描述： | 110 MSPS/140 MSPS的模擬接口的平板顯示器 |
| 文件頁數(shù)： | 17/32頁 |
| 文件大?。?/td> | 344K |
| 代理商： | AD9985A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當(dāng)前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
AD9985A
2-WIRE SERIAL REGISTER MAP
The AD9985A is initialized and controlled by a set of registers that determine the operating modes. An external controller is used to write
and read the control registers through the two-line serial interface port.
Table 10. Control Register Map
Write and
Read or
Read-Only
Bits
Value
Name
0x00
RO
7:0
Chip Revision
0x01
1
R/W
7:0
01101001
PLL Div MSB
Rev. 0 | Page 17 of 32
Hexadecimal
Address
Default
Register
Function
An 8-bit register that represents the silicon revision level.
This register is for Bits [11:4] of the PLL divider. Greater values mean
the PLL operates at a faster rate. This register should be loaded first
whenever a change is needed. This will give the PLL more time to lock.
Bits [7:4] of this word are written to the LSBs [3:0] of the PLL divider
word.
Bits [7:6] VCO Range. Selects VCO frequency range. (See the PLL
description.)
Bits [5:3] Charge Pump Current. Varies the current that drives the
low-pass filter. (See the PLL description.)
ADC Clock Phase Adjustment. Larger values mean more delay.
(1 LSB = T/32)
Places the clamp signal an integer number of clock periods after the
trailing edge of the Hsync signal.
Number of clock periods that the clamp signal is actively clamping.
0x02
1
R/W
7:4
1101****
PLL Div LSB
0x03
R/W
7:3
01******
**001***
0x04
R/W
7:3
10000***
Phase Adjust
0x05
R/W
7:0
10000000
Clamp
Placement
Clamp
Duration
Hsync Output
Pulse Width
Red Gain
Green Gain
Blue Gain
Red Offset
Green Offset
Blue Offset
Sync Control
0x06
7:0
10000000
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
R/W
7:0
00100000
Sets the number of pixel clocks that HSOUT will remain active.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7:0
7:0
7:0
7:1
7:1
7:1
7:0
10000000
10000000
10000000
1000000*
1000000*
1000000*
0*******
Controls the ADC input range (contrast) of each respective channel.
Greater values give less contrast.
Controls dc offset (brightness) of each respective channel. Greater
values decrease brightness.
Bit 7—Hsync Polarity Override. (Logic 0 = polarity determined by
chip, Logic 1 = polarity set by Bit 6 in Register 0x0E.)
Bit 6—Hsync Input Polarity. Indicates polarity of incoming Hsync
signal to the PLL. (Logic 0 = active low, Logic 1 = active high.)
Bit 5—Hsync Output Polarity. (Logic 0 = logic high sync,
Logic 1 = logic low sync.)
Bit 4—Active Hsync Override. If set to Logic 1, the user can select the
Hsync to be used via Bit 3. If set to Logic 0, the active interface is
selected via Bit 6 in Register 0x14.
Bit 3—Active Hsync Select. Logic 0 selects Hsync as the active sync.
Logic 1 selects sync-on-green as the active sync. Note that the
indicated Hsync is used only if Bit 4 is set to Logic 1 or if both syncs
are active. (Bits 1, 7 = Logic 1 in Register 0x14.)
Bit 2—Vsync Output Invert. (Logic 1 = no invert, Logic 0 = invert.)
Bit 1—Active Vsync Override. If set to Logic 1, the user can select the
Vsync to be used via Bit 0. If set to Logic 0, the active interface is
selected via Bit 3 in Register 0x14.
Bit 0—Active Vsync Select. Logic 0 selects raw Vsync as the output
Vsync. Logic 1 selects sync separated Vsync as the output Vsync.
Note that the indicated Vsync is used only if Bit 1 is set to Logic 1.
Bit 7—Clamp Function. Chooses between Hsync for clamp signal or
another external signal to be used for clamping. (Logic 0 = Hsync,
Logic 1 = Clamp.)
*1******
**0*****
***0****
****0***
*****0**
******0*
*******0
0x0F
R/W
7:1
0*******
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9985ABSTZ-110 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9985AKSTZ-110 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9985AKSTZ-140 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9985BSTZ-110 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9985 | 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9985A/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
| AD9985A/PCBZ | 功能描述:KIT EVALUATION FOR AD9985A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:Advantiv® 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| AD9985AABSTZ-110 | 制造商:Analog Devices 功能描述:ANALOG INTERFACE FOR FLAT PANEL DISPLAYS - Bulk |
| AD9985AAKSTZ-110 | 制造商:Analog Devices 功能描述:ANALOG INTERFACE FOR FLAT PANEL DISPLAYS - Bulk |
| AD9985AAKSTZ-140 | 制造商:Analog Devices 功能描述:ANALOG INTERFACE FOR FLAT PANEL DISPLAYS - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。