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參數(shù)資料
| 型號： | AD9983AKSTZ-1401 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | High Performance 8-Bit Display Interface |
| 中文描述： | 高性能8位顯示接口 |
| 文件頁數(shù)： | 19/44頁 |
| 文件大小： | 470K |
| 代理商： | AD9983AKSTZ-1401 |
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Preliminary Technical Data
AD9983A
POWER MANAGEMENT
To meet display requirements for low standby power, the
AD9983A includes a power-down mode. The power-down state
can be controlled manually (via Pin 17 or Register 0x1E, Bit 3),
or automatically by the chip. If automatic control is selected
(Register 0x1E, Bit 4), the AD9983A decision is based on the
status of the sync detect bits (Register 0x24, Bit 2, Bit 3, Bit 6,
and Bit 7). If either an Hsync or a sync-on-green input is
detected on any input, the chip powers up, otherwise it powers
down. For manual control, the AD9983A allows flexibility of
control through both a dedicated pin and a register bit. The
dedicated pin allows a hardware watchdog circuit to control
power-down, while the register bit allows power-down to be
controlled by software. With manual power-down control, the
polarity of the power-down pin must be set (Register 0x1E, Bit 2)
whether the pin is used or not. If unused, it is recommended to
set the polarity to active high and hardwire the pin to ground with
a 10 kΩ resistor.
Rev. PrA | Page 19 of 44
In power-down mode, there are several circuits that continue to
operate as normal. The serial register and sync detect circuits
maintain power so that the AD9983A can be woken up from
its power-down state. The bandgap circuit maintains power
because it is needed for sync detection. The sync-on-green and
SOGOUT functions continue to operate because the SOGOUT
output is needed when sync detection is performed by a
secondary chip. All of these circuits require minimal power to
operate. Typical standby power on the AD9983A is about 50 mW
There are two options that can be selected when in power-
down. These are controlled by Bit 0 and Bit 1 in Register 0x1E.
Bit 0 controls whether the SOGOUT pin is in high impedance
impedance during normal operation. The option to put
SOGOUT in high impedance is included mainly to allow for
factory testing modes. Bit 1 keeps the AD9983A powered up
while placing only the outputs in high impedance. This option
is useful when the data outputs from two chips are connected
on a PCB and the user wants to switch instantaneously between
the two.
Table 11. Power-Down Control and Mode Descriptions
Inputs
Mode
Power-Up
Power-Down
Auto Power-Down
Control
1
1
1
Power-Down
2
X
X
Sync Detect
3
1
0
Powered On/Comments
Everything
Only the serial bus, sync activity detect,
SOG, bandgap reference
Everything
Only the serial bus, sync activity detect,
SOG, bandgap reference
Power-Up
Power-Down
0
0
0
1
X
X
1
Auto power-down control is set by Register 0x1E, Bit 4.
2
Power-down is controlled by OR’ing Pin 17 with Register 0x1E, Bit 3. The polarity of Pin 17 is set by Register 0x1E, Bit 2.
3
Sync detect is determined by OR’ing Register 0x24, Bit 2, Bit 3, Bit 6, and Bit 7.
TIMING DIAGRAMS
The timing diagrams in Figure 14 to Figure 17 show the operation of the AD9983A. The output data clock signal is created so that its
rising edge always occurs between data transitions and can be used to latch the output data externally. There is a pipeline in the
AD9983A, which must be flushed before valid data becomes available. This means six data sets are presented before valid data is available.
t
PER
t
DCYCLE
t
SKEW
DATACK
DATA
HSOUT
0
Figure 14. Output Timing
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