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參數(shù)資料
| 型號(hào)： | AD9983AKSTZ-1401 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | High Performance 8-Bit Display Interface |
| 中文描述： | 高性能8位顯示接口 |
| 文件頁數(shù)： | 13/44頁 |
| 文件大小： | 470K |
| 代理商： | AD9983AKSTZ-1401 |
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Preliminary Technical Data
AD9983A
Negative target codes are included in order to duplicate a fea-
ture that is present with manual offset adjustment. The benefit
that is being mimicked is the ability to easily adjust brightness
on a display. By setting the target code to a value that does not
correspond to the ideal ADC range, the end result is an image
that is either brighter or darker. A target code higher than ideal
results in a brighter image. A target code lower than ideal
results in a darker image.
The ability to program a target code gives a large degree of
freedom and flexibility. In most cases all channels are set to
either 1 or 128, but the flexibility to select other values allows
for the possibility of inserting intentional skews between
channels. It also allows the ADC range to be skewed so that
voltages outside of the normal range can be digitized. For
example, setting the target code to 40 allows the sync tip, which
is normally below black level, to be digitized and evaluated.
The internal logic for the auto-offset circuit requires 16 data
clock cycles to perform its function. This operation is executed
immediately after the clamping pulse. Therefore, it is important
to end the clamping pulse signal at least 16 data clock cycles
before active video. This is true whether using the AD9983A
internal clamp circuit or an external clamp signal. The auto-
offset function can be programmed to run continuously or on a
one-time basis (see auto-offset hold, Register 0x2C, Bit 4). In
continuous mode, the update frequency can be programmed
(Register 0x1B, Bits[4:3]). Continuous operation with updates
every 64 Hsyncs is recommended.
A guideline for basic auto-offset operation is shown in Table 6
and Table 7.
Rev. PrA | Page 13 of 44
Table 6. RGB Auto-Offset Register Settings
Register
Value
0x0B
0x02
0x0C
0x00
0x0D
0x02
0x0E
0x00
0x0F
0x02
0x10
0x00
0x18, Bits[3:1]
000
Comments
Sets red target to 4
Must be written
Sets green target to 4
Must be written
Sets blue target to 4
Must be written
Sets red, green, and blue
channels to ground clamp
Selects update rate and
enables auto-offset.
0x1B, Bits[5:3]
110
Table 7. PbPr Auto-Offset Register Settings
Register
Value
0x0B
0x40
0x0C
0x00
0x0D
0x02
0x0E
0x00
0x0F
0x40
0x10
0x00
0x18 Bits[3:1]
101
Comments
Sets Pr (red) target to 128
Must be written
Sets Y (green) target to 4
Must be written
Sets Pb (blue) target to 128
Must be written
Sets Pb, Pr to midscale clamp
and Y to ground clamp
Selects update rate and
enables auto-offset
0x1B, Bits[5:3]
110
Automatic Gain Matching
The AD9983A includes circuitry to match the gains between
the three channels to within 1% of each other. Matching the
gains of each channel is necessary in order to achieve good
color balance on a display. On products without this feature,
gain matching is achieved by writing software that evaluates the
output of each channel, calculates gain mismatches, then writes
values to the gain registers of each channel to compensate. With
the auto gain matching function, this software routine is no
longer needed. To activate auto gain matching, set Register 0x3C,
Bit 2 to Bit 1.
Auto gain matching has similar timing requirements to auto
offset. It requires 16 data clock cycles to perform its function,
starting immediately after the end of the clamp pulse. Unlike
auto offset it does not require that these 16 clock cycles occur
during the back porch reference time, although that is what is
recommended. During auto gain matching operation, the data
outputs of the AD9983A are frozen (held at the value they had
just prior to operation). The auto gain matching function can be
programmed to run continuously or on a one-time basis (see
Auto Gain Matching Hold section, Register 0x2C, Bit 3). In
continuous mode, the update frequency can be programmed
(Register 0x1B, Bit 4 and Bit 3). Continuous operation with
updates every 64 Hsyncs is recommended.
SYNC-ON-GREEN
The sync-on-green inputs (SOGIN0, SOGIN1) operate in two
steps. First, they set a baseline clamp level off of the incoming
video signal with a negative peak detector. Second, they set the
sync trigger level to a programmable (Register 0x1D, Bits[7:3])
level (typically 128 mV) above the negative peak. The sync-on-
green inputs must be ac-coupled to the green analog input
through their own capacitors. The value of the capacitors must
be 1 nF ±20%. If sync-on-green is not used, this connection is
not required. The sync-on-green signal always has negative
polarity.
R
AIN
B
AIN
G
AIN
SOGIN
47nF
47nF
47nF
1nF
0
Figure 5. Typical Input Configuration
REFERENCE BYPASSING
REFLO and REFHI are connected to each other by a 10 μF
capacitor. These references are used by the input ADC circuitry.
REFHI
REFLO
10μF
0
Figure 6. Input Amplifier Reference Capacitors
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