- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373972 > AD9981KSTZ-95 (ANALOG DEVICES INC) High Performance 10-Bit Display Interface PDF資料下載
參數(shù)資料
| 型號： | AD9981KSTZ-95 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 其它接口 |
| 英文描述： | High Performance 10-Bit Display Interface |
| 中文描述： | SPECIALTY INTERFACE CIRCUIT, PQFP80 |
| 封裝： | LEAD FREE, MS-026BEC, LQFP-80 |
| 文件頁數(shù)： | 14/44頁 |
| 文件大?。?/td> | 506K |
| 代理商： | AD9981KSTZ-95 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當(dāng)前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
AD9981
Rev. 0 | Page 14 of 44
PIXEL CLOCK
INVALID SAMPLE TIMES
0
Figure 6. Pixel Sampling Times
Any jitter in the clock reduces the precision with which the
sampling time can be determined and must also be subtracted
from the stable pixel time. Considerable care has been taken in
the design of the AD9981’s clock generation circuit to minimize
jitter. The clock jitter of the AD9981 is 9% or less of the total
pixel time in all operating modes, making the reduction in the
valid sampling time due to jitter negligible.
The PLL characteristics are determined by the loop filter design,
the PLL charge pump current, and the VCO range setting. The
loop filter design is illustrated in Figure 7. Recommended
settings of the VCO range and charge pump current for VESA
standard display modes are listed in Table 9.
C
P
8nF
C
80nF
R
Z
1.5k
FILT
PV
D
0
Figure 7. PLL Loop Filter Detail
Four programmable registers are provided to optimize the
performance of the PLL. These registers are
1.
The 12-Bit Divisor Register. The input Hsync frequencies
can accommodate any Hsync as long as the product of the
Hsync and the PLL divisor falls within the operating range
of the VCO. The PLL multiplies the frequency of the Hsync
signal, producing pixel clock frequencies in the range of
10 MHz to 95 MHz. The divisor register controls the exact
multiplication factor. This register may be set to any value
between 2 and 4095 as long as the output frequency is
within range.
2.
The 2-Bit VCO Range Register. To improve the noise
performance of the AD9981, the VCO operating frequency
range is divided into four overlapping regions. The VCO
range register sets this operating range. The frequency
ranges for the four regions are shown in Table 7.
Table 7. VCO Frequency Ranges
Pixel Clock
Range (MHz)
0
0
10–21
0
1
21–42
1
0
42–84
1
1
84-95
PV1
PV0
KVCO
Gain (MHz/V)
150
150
150
150
3.
The 3-Bit Charge Pump Current Register. This register
varies the current that drives the low-pass loop filter. The
possible current values are listed in Table 8.
Table 8. Charge Pump Current/Control Bits
Ip2
Ip1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Ip0
0
1
0
1
0
1
0
1
Current (μA)
50
100
150
250
350
500
750
1500
4.
The 5-Bit Phase Adjust Register. The phase of the gen-
erated sampling clock may be shifted to locate an optimum
sampling point within a clock cycle. The phase adjust
register provides 32 phase-shift steps of 11.25° each. The
Hsync signal with an identical phase shift is available
through the HSOUT pin. Phase adjust is still available if an
external pixel clock is used. The COAST pin or the internal
Coast is used to allow the PLL to continue to run at the
same frequency in the absence of the incoming Hsync
signal or during disturbances in Hsync (such as from
equalization pulses). This may be used during the vertical
sync period or at any other time that the Hsync signal is
unavailable. The polarity of the Coast signal may be set
through the Coast polarity register (Register 0x18,
Bits [6:5]). Also, the polarity of the Hsync signal may
be set through the Hsync polarity register (Register 0x12,
Bits [5:4]). For both Hsync and Coast, a value of 1 is active
high. The internal Coast function is driven off the Vsync
signal, which is typically a time when Hsync signals may be
disrupted with extra equalization pulses.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9983AKSTZ-140 | High Performance 8-Bit Display Interface |
| AD9983AKSTZ-1401 | High Performance 8-Bit Display Interface |
| AD9983AKSTZ-170 | High Performance 8-Bit Display Interface |
| AD9983AKSTZ-1701 | High Performance 8-Bit Display Interface |
| AD9983A | High Performance 8-Bit Display Interface |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9981XSTZ-110 | 制造商:Analog Devices 功能描述:HIGH PERFORMANCE 10-BIT DISPLAY INTERFACE - Bulk |
| AD9983A | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance 8-Bit Display Interface |
| AD9983A/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance 8-Bit Display Interface |
| AD9983A/PCBZ | 功能描述:KIT EVALUATION AD9983A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:Advantiv® 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| AD9983AKCPZ-140 | 功能描述:IC INTRFACE 8BIT 140MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。