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參數(shù)資料
| 型號： | AD9981KSTZ-95 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 其它接口 |
| 英文描述： | High Performance 10-Bit Display Interface |
| 中文描述： | SPECIALTY INTERFACE CIRCUIT, PQFP80 |
| 封裝： | LEAD FREE, MS-026BEC, LQFP-80 |
| 文件頁數(shù)： | 12/44頁 |
| 文件大?。?/td> | 506K |
| 代理商： | AD9981KSTZ-95 |
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AD9981
In most PC graphics systems, black is transmitted between
active video lines. With CRT displays, when the electron beam
has completed writing a horizontal line on the screen (at the
right side), the beam is deflected quickly to the left side of the
screen (called horizontal retrace) and a black signal is provided
to prevent the beam from disturbing the image.
Rev. 0 | Page 12 of 44
In systems with embedded sync, a blacker-than-black signal
(Hsync) is produced briefly to signal the CRT that it is time to
begin a retrace. Because the input is not at black level at this
time, it is important to avoid clamping during Hsync. Fortu-
nately, there is virtually always a period following Hsync, called
the ‘back porch’ where a good black reference is provided. This
is the time when clamping should be done.
The clamp timing can be established by simply exercising the
CLAMP pin at the appropriate time with clamp source
(Register 0x18, Bit 4) = 1. The polarity of this signal is set by
the clamp polarity bit (Register 0x1B, Bits [7:6]).
A simpler method of clamp timing employs the AD9981
internal clamp timing generator. The clamp placement register
(Register 0x19) is programmed with the number of pixel
periods that should pass after the trailing edge of Hsync
before clamping starts. A second register, clamp duration,
(Register 0x1A) sets the duration of the clamp. These are both
8-bit values, providing considerable flexibility in clamp
generation. The clamp timing is referenced to the trailing edge
of Hsync because, though Hsync duration can vary widely, the
back porch (black reference) always follows Hsync. A good
starting point for establishing clamping is to set the clamp
placement to 0x04 (providing 4 pixel periods for the graphics
signal to stabilize after sync) and set the clamp duration to
0x28 (giving the clamp 40 pixel periods to reestablish the
black reference).
Clamping is accomplished by placing an appropriate charge on
the external input coupling capacitor. The value of this capacitor
affects the performance of the clamp. If it is too small, there will
be a significant amplitude change during a horizontal line time
(between clamping intervals). If the capacitor is too large, then
it will take excessively long for the clamp to recover from a large
change in incoming signal offset. The recommended value
(47 nF) results in recovering from a step error of 100 mV to
within 1 LSB in 30 lines with a clamp duration of 20 pixel
periods on a 85 Hz XGA signal.
YPbPr Clamping
YPbPr graphic signals are slightly different from RGB signals in
that the dc reference level (black level in RGB signals) of color
difference signals is at the midpoint of the video signal rather
than at the bottom. The three inputs are composed of
luminance (Y) and color difference (Pb and Pr) signals. For
color difference signals it is necessary to clamp to the midscale
range of the ADC range (512) rather than to the bottom of the
ADC range (0), while the Y channel is clamped to ground.
Clamping to midscale rather than ground can be accomplished
by setting the clamp select bits in the serial bus register. Each of
the three converters has its own selection bit so that they can be
independently clamped to either midscale or ground. These bits
are located in Register 0x18, Bits [3:1]. The midscale reference
voltage is internally generated for each converter.
GAIN AND OFFSET CONTROL
The AD9981 contains three programmable gain amplifiers
(PGAs), one for each of the three analog inputs. The range of
the PGA is sufficient to accommodate input signals with inputs
ranging from 0.5 V to 1.0 V full scale. The gain is set in three
9-bit registers (red gain [0x05, 0x06], green gain [0x07, 0x08],
blue gain [0x09, 0x0A]). For each of these registers, a gain
setting of 0 corresponds to the highest gain, while a gain setting
of 511 corresponds to the lowest gain. Note that increasing the
gain setting results in an image with less contrast.
The offset control shifts the analog input, resulting in a change
in brightness. Three 11-bit registers (red offset [0x0B, 0x0C],
green offset [0x0D, 0x0E], blue offset [0x0F, 0x10]) provide
independent settings for each channel. Note that the function of
the offset register depends on whether auto-offset is enabled
(Register 0x1B, Bit 5).
If manual offset is used, nine bits of the offset registers (for
the red channel Register 0x0B, Bits [6:0] plus Register 0x0C,
Bits [7:6]) control the absolute offset added to the channel. The
offset control provides ±255 LSBs of adjustment range, with one
LSB of offset corresponding to one LSB of output code.
Automatic Offset
In addition to the manual offset adjustment mode, the AD9981
also includes circuitry to automatically calibrate the offset for
each channel. By monitoring the output of each ADC during
the back porch of the input signals, the AD9981 can self-adjust
to eliminate any offset errors in its own ADC channels and any
offset errors present on the incoming graphics or video signals.
To activate the auto-offset mode, set Register 0x1B, Bit 5 to 1.
Next, the target code registers (0x0B through 0x10) must be
programmed. The values programmed into the target code
registers should be the output code desired from the AD9981
during the back porch reference time. For example, for RGB
signals, all three registers would normally be programmed to
Code 1, while for YPbPr signals the green (Y) channel is nor-
mally set to Code 1 and the blue and red channels (Pb and Pr)
are set to 512. The target code registers have 11 bits per channel
and are in twos complement format. This allows any value
between –1024 and +1023 to be programmed. Although any
value in this range can be programmed, the AD9981’s offset
range may not be able to reach every value. Intended target code
values range from (but are not limited to) –160 to –1 and +1 to
+160 when ground clamping, and +350 to +670 when midscale
clamping. Note that a target code of 0 is not valid.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9981XSTZ-110 | 制造商:Analog Devices 功能描述:HIGH PERFORMANCE 10-BIT DISPLAY INTERFACE - Bulk |
| AD9983A | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance 8-Bit Display Interface |
| AD9983A/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance 8-Bit Display Interface |
| AD9983A/PCBZ | 功能描述:KIT EVALUATION AD9983A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:Advantiv® 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| AD9983AKCPZ-140 | 功能描述:IC INTRFACE 8BIT 140MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
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