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參數(shù)資料
| 型號： | AD995PCBZ |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC |
| 中文描述： | 1 GSPS的正交數(shù)字上變頻器w/18-Bit智商數(shù)據(jù)路徑和14位DAC |
| 文件頁數(shù)： | 9/38頁 |
| 文件大?。?/td> | 602K |
| 代理商： | AD995PCBZ |
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PRELIMINARY TECHNICAL DATA
AD9957
Rev. PrF | Page 9 of 38
59
I/O_UPDATE
I
Digital input (active high). Input/Output update: A high on this pin transfers the
contents of the I/O buffers to the corresponding internal registers.
Digital input (active high). Output shaped keying: When the OSK features (manual or
automatic), this device controls the OSK function. In manual mode, it toggles the
multiplier between 0 (low) and the programmed amplitude scale factor (high). In
automatic mode, a low sweeps the amplitude down to zero, a high sweeps the
amplitude up to the amplitude scale factor.
Digital input/output (active high). Serial data input/output: this pin can be either uni-
directional or bidirectional (default), depending on configuration settings. In
bidirectional serial port mode, this pin acts as the serial data input and output. In
unidirectional, it is an input only.
Digital output (active high). Serial Data output: this pinis only active in unidirectional
serial data mode. In this mode, it functions as the output. In bidirectional mode, this
pin is not operational and should be left floating.
Digital clock (rising edge on write, falling edge on read). Serial data clock: this pin
provides the serial data clock for the control data path. Write operations to the
AD9957 use the rising edge. Readback operations from the AD9957 use the falling
edge.
Digital input (active low) Chip Select: Bringing this pin low enables the AD9957 to
detect serial clock rising/falling edges. Bringing this pin high will cause the AD9957 to
ignore input on the serial data pins.
Digital input (active high) I/O Reset: Rather than resetting the entire device during a
failed communication cycle, when brought high this pin will reset the state machine of
the serial port controller and clear any I/O buffers that have been written since the last
I/O Update. When unused, tie this pin to ground to avoid accidental resets.
Analog output (current mode): Open source DAC complementary output source.
Connect through 50Ω to AGND.
Analog output (current mode): Open source DAC output source. Connect through
50Ω to AGND.
Analog reference pin: programs the DAC output full scale reference current. Attach a
10KΩ resistor to AGND.
Analog input(active high): Reference CLK input. Can be driven by either an external
oscillator or a simple crystal when the internal oscillator is engaged.
Analog input(active high): Reference CLK input
Analog output (active high). Crystal Output: Provides the output of the internal
oscillator’s response to a crystal.
Crystal Select:
selects the reference clock input mode when using the on-
chip PLL. Pulling this pin low allows the user to provide a reference clock
input to the PLL from an external source. Pulling this pin high enables
the on-chip XTAL buffer and allows the user to drive the reference input
clock with a crystal
60
OSK
I
67
SDIO
I/O
68
SDO
O
69
SCLK
O
70
CS
I
71
I/O_RESET
I
80
IOUT
O
81
IOUT
O
84
DAC_RSET
O
90
REF_CLK
I
91
94
REF_CLK
XTAL_OUT
I
O
95
XTAL_SEL
O
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