- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375249 > AD995PCBZ (Analog Devices, Inc.) 1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC PDF資料下載
參數(shù)資料
| 型號(hào)： | AD995PCBZ |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC |
| 中文描述： | 1 GSPS的正交數(shù)字上變頻器w/18-Bit智商數(shù)據(jù)路徑和14位DAC |
| 文件頁(yè)數(shù)： | 32/38頁(yè) |
| 文件大小： | 602K |
| 代理商： | AD995PCBZ |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)當(dāng)前第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)
AD9957
PRELIMINARY TECHNICAL DATA
Rev. PrF | Page 32 of 38
REGISTER DESCRIPTIONS
Control Function Register #1 (CFR1)
The CFR1 is comprised of four bytes located in address 00h.
CFR1<31>
:
RAM Enable bit
.
When
CFR1<31>
= 0
(default),
disables the RAM putting
it in the lowest power state (unless being written to via
the serial port).
When
CFR1<31>
= 1, enables the RAM.
CFR1<30:29>
:
OPEN
. Always leave these bits clear.
CFR1<28>
:
RAM QDUC Evaluation Enable bi
t.
When
CFR1<28>
= 0
(default)
, The RAM QDUC
evaluation mode of the device is inactive.
When
CFR1<28>
= 1, The RAM QDUC evaluation
mode is activated, if the RAM Enable bit is set. When in
the RAM QDUC Evaluation mode the input data port is
disengaged form the signal processing path and the
RAM drives the I and Q data at the IQ sample rate.
CFR1<27:26>
:
OPEN
. Always leave these bits clear.
CFR1<25:24>
:
QDUC Operating Mode bits
.
The CFR1<25:24> bits set the mode of operation:
CFR1<25:24>
Mode of Operation
00 (
default
)
Quadrature Modulation
01
Single Tone
1x
Interpolating DAC
CFR1<23>
:
Manual OSK External Control
.
Note, this bit is ignored unless manual OSK mode is se-
lected using CFR1<9:8>.
When
CFR1<23>
= 0
(default)
, the manual OSK mode
does not require the use of the OSK input pin to operate.
When
CFR1<23>
= 1, the manual OSK mode uses the
OSK input pin. See pin description.
CFR1<22>
:
Inverse Sinc Enable bit
.
When
CFR1<22>
= 0
(default)
, the inverse sinc filter is
inactive - the local clock is stopped to save power. The
input data is passed directly to the output of the filter.
When
CFR1<22>
= 1, the inverse sinc filter is enabled
and operational.
CFR1<21>
:
Clear CCI bit
.
When
CFR1<21>
= 0
(default)
, the CCI filter operates
normally.
When
CFR1<21>
= 1, The CCI filter is asynchronously
cleared.
CFR1<20:17>
:
Internal Profile Control bits
.
These bits cause the Profile Bits to be ignored and put
the device into an automatic “profile loop sequence” that
allows the user to implement a frequency/phase compos-
ite sweep that runs without external inputs.
CFR1<16>
:
Sine Enable bit
.
When
CFR1<16> = 0
(default)
, the angle-to-amplitude
conversion logic outputs a COSINE function.
When CFR1<16> = 1, the angle-to-amplitude conver-
sion logic outputs a SINE function.
CFR1<15:14>
:
OPEN
. Always leave these bits clear.
CFR1<13>: Auto Clear Phase Accumulator
When CFR1<13> = 0
(default)
,
)
, the accumulation
function is not interrupted.
When CFR1<13> = 1, this bit automatically and syn-
chronously clears (loads zeros into) the phase accumula-
tor for one cycle upon receipt of the I/O UPDATE se-
quence indicator.
CFR1<12>: OPEN
. Always leave this bit clear.
CFR1<11>: Clear Phase Accumulator
When CFR1<11> = 0
(default)
, the phase accumulator
functions as normal.
When CFR1<11> = 1, the phase accumulator memory
element is asynchronously cleared.
CFR1<10>
:
Load Amplitude Rate Register @ IOUpdate
When CFR1<10> = 0
(default)
, the amplitude ramp rate
timer is loaded only upon timeout (timer ==1); it is not
loaded due to an I/O UPDATE input signal (or change
in profile).
When CFR1<10> = 1, the amplitude ramp rate timer is
loaded upon timeout (timer ==1) or at the time of an
I/O UPDATE input signal (or change in profile).
CFR1<9>
:
Output Shaped Keying Enable
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9959 | 4 Channel 500MSPS DDS with 10-bit DACs |
| AD9979 | 14-Bit, CCD Signal Processor with Precision Timing Core |
| AD9980 | High Performance 8-Bit Display Interface |
| AD9980KSTZ-80 | High Performance 8-Bit Display Interface |
| AD9980KSTZ-95 | High Performance 8-Bit Display Interface |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9960BSTZ | 功能描述:RFID應(yīng)答器 MxFE for RFID Reader Transceiver RoHS:否 制造商:Murata 存儲(chǔ)容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| AD9960BSTZRL | 功能描述:IC MXFE FOR RFID READER/TXRX RoHS:是 類別:RF/IF 和 RFID >> RFID IC 系列:AD9960B 其它有關(guān)文件:CR14 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- RF 型:收發(fā)器 頻率:13.56MHz 特點(diǎn):ISO14443-B 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SO 包裝:Digi-Reel® 其它名稱:497-5719-6 |
| AD9960XSTZ | 制造商:Analog Devices 功能描述:SINGLE-SUPPLY CABLE MODEM/SET-TOP BOX MIXED-SIGNAL FRONT END - Trays |
| AD9961 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-/12-Bit, Low Power, Broadband MxFE |
| AD9961_12 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-/12-Bit, Low Power, Broadband MxFE |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。